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PIC16C7X
DS30390D-page 302
1996 Microchip Technology Inc.
Figure 4-16:
PIR1 Register PIC16C73/73A/74/74A
(Address 0Ch)...........................................37
PIE2 Register (Address 8Dh)....................38
PIR2 Register (Address 0Dh)....................39
PCON Register (Address 8Eh) .................40
Loading of PC In Different Situations........41
Direct/Indirect Addressing.........................42
Block Diagram of RA3:RA0 and
RA5 Pins ...................................................43
Block Diagram of RA4/T0CKI Pin .............44
Block Diagram of RB3:RB0 Pins...............45
Block Diagram of RB7:RB4 Pins
(PIC16C71/73/74) .....................................46
Block Diagram of RB7:RB4 Pins
(PIC16C710/711/72/73A/74A) ..................46
PORTC Block Diagram
(Peripheral Output Override).....................48
PORTD Block Diagram
(in I/O Port Mode)......................................50
TRISE Register (Address 89h)..................52
PORTE Block Diagram
(in I/O Port Mode)......................................53
Successive I/O Operation .........................54
PORTD and PORTE Block Diagram
(Parallel Slave Port) ..................................55
Timer0 Block Diagram...............................59
Timer0 Timing: Internal Clock/
No Prescale...............................................59
Timer0 Timing: Internal Clock/
Prescale 1:2 ..............................................60
Timer0 Interrupt Timing.............................60
Timer0 Timing with External Clock............61
Block Diagram of the Timer0/WDT
Prescaler...................................................62
T1CON: Timer1 Control Register
(Address 10h)............................................65
Timer1 Block Diagram...............................66
Timer2 Block Diagram...............................69
T2CON: Timer2 Control Register
(Address 12h)............................................70
CCP1CON Register (Address 17h)/
CCP2CON Register (Address 1Dh)..........72
Capture Mode Operation Block Diagram ..72
Compare Mode Operation
Block Diagram...........................................73
Simplified PWM Block Diagram ................74
PWM Output..............................................74
SSPSTAT: Sync Serial Port Status
Register (Address 94h) .............................77
SSPCON: Sync Serial Port Control
Register (Address 14h) .............................78
SSP Block Diagram (SPI Mode) ...............79
SPI Master/Slave Connection ...................80
SPI Mode Timing (Master Mode
or Slave Mode w/o ss Control)..................81
SPI Mode Timing (Slave Mode
with ss Control) .........................................81
Start and Stop Conditions .........................83
7-bit Address Format.................................84
I
C 10-bit Address Format ........................84
Slave-receiver Acknowledge.....................84
Data Transfer Wait State...........................84
Master-transmitter Sequence....................85
Master-receiver Sequence........................85
Combined Format .....................................85
Multi-master Arbitration (Two Masters).....86
Figure 4-17:
Figure 4-18:
Figure 4-19:
Figure 4-20:
Figure 4-21:
Figure 5-1:
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Figure 5-11:
Figure 7-1:
Figure 7-2:
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Figure 8-1:
Figure 8-2:
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Figure 11-13:
Figure 11-14:
Figure 11-15:
2
Figure 11-16:
Figure 11-17:
Figure 11-18:
Clock Synchronization .............................. 86
SSP Block Diagram (I
I
C Waveforms for Reception
(7-bit Address) .......................................... 89
I
C Waveforms for Transmission
(7-bit Address) .......................................... 90
Operation of the I
C Module in
IDLE_MODE, RCV_MODE or
XMIT_MODE ............................................ 92
TXSTA: Transmit Status and
Control Register (Address 98h) ................ 93
RCSTA: Receive Status and
Control Register (Address 18h) ................ 94
RX Pin Sampling Scheme (BRGH = 0)..... 98
RX Pin Sampling Scheme (BRGH = 1)..... 98
RX Pin Sampling Scheme (BRGH = 1)..... 98
USART Transmit Block Diagram .............. 99
Asynchronous Master Transmission....... 100
Asynchronous Master Transmission
(Back to Back) ........................................ 100
USART Receive Block Diagram ............. 101
Asynchronous Reception........................ 101
Synchronous Transmission .................... 104
Synchronous Transmission
(Through TXEN) ..................................... 104
Synchronous Reception
(Master Mode, SREN) ............................ 106
ADCON0 Register, PIC16C710/71/711
(Address 08h) ......................................... 109
ADCON0 Register, PIC16C72/73/73A/
74/74A (Address 1Fh)............................. 110
ADCON1 Register for
PIC16C710/71/711 (Address 88h).......... 110
ADCON1 Register, PIC16C72/73/73A/
74/74A (Address 9Fh)............................. 111
A/D Block Diagram,
PIC16C710/71/711................................. 112
A/D Block Diagram,
PIC16C72/73/73A/74/74A ...................... 113
Analog Input Model................................. 114
A/D Transfer Function............................. 119
Flowchart of A/D Operation .................... 119
Configuration Word for PIC16C71.......... 121
Configuration Word for PIC16C710/711. 122
Configuration Word for PIC16C73/74..... 122
Configuration Word for
PIC16C72/73A/74A ................................ 123
Crystal/Ceramic Resonator Operation
(HS, XT or LP
OSC Configuration) ................................ 123
External Clock Input Operation
(HS, XT or LP OSC Configuration)......... 123
External Parallel Resonant Crystal
Oscillator Circuit...................................... 125
External Series Resonant Crystal
Oscillator Circuit...................................... 125
RC Oscillator Mode................................. 125
Simplified Block Diagram of
On-chip Reset Circuit.............................. 126
Brown-out Situations............................... 127
Time-out Sequence on Power-up
(MCLR not Tied to V
DD
Time-out Sequence on Power-up
(MCLR Not Tied To V
DD
Time-out Sequence on Power-up
(MCLR Tied to V
DD
)................................ 131
2
C Mode)................ 87
2
Figure 11-19:
2
Figure 11-20:
2
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Figure 14-8:
Figure 14-9:
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Figure 14-11:
Figure 14-12:
): Case 1 ............ 131
Figure 14-13:
): Case 2 .......... 131
Figure 14-14: