![](http://datasheet.mmic.net.cn/260000/PIC16C710_datasheet_15942818/PIC16C710_41.png)
1996 Microchip Technology Inc.
DS30390D-page 41
PIC16C7X
4.3
PCL and PCLATH
Applicable Devices
710 71 711 72 73 73A 74 74A
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any reset, the PC is cleared. Figure 4-20 shows the
two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH<4:0>
→
PCH). The lower exam-
ple in the figure shows how the PC is loaded during a
CALL
or
GOTO
instruction (PCLATH<4:3>
→
PCH).
FIGURE 4-20: LOADING OF PC IN
DIFFERENT SITUATIONS
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (
ADDWF PCL
). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read"(AN556).
4.3.2
STACK
The PIC16CXX family has an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a
CALL
instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW
or a
RETFIE
instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
PC
12
8
7
0
5
PCLATH<4:0>
PCLATH
Instruction with
PCL as
Destination
ALU result
GOTO, CALL
Opcode <10:0>
8
PC
12
11 10
0
11
PCLATH<4:3>
PCH
PCL
8
7
2
PCLATH
PCH
PCL
4.4
Program Memory Paging
Applicable Devices
710 71 711 72 73 73A 74 74A
The PIC16C73/73A and the PIC16C74/74A have 4K of
program memory, but the
CALL
and
GOTO
instructions
only have a 11-bit address range. This 11-bit address
range allows a branch within a 2K program memory
page size. To allow
CALL
and
GOTO
instructions to
address the entire 4K program memory address range,
there must be another bit to specify the program mem-
ory page. This paging bit comes from the PCLATH<3>
bit (Figure 4-20). When doing a
CALL
or
GOTO
instruc-
tion, the user must ensure that this page bit
(PCLATH<3>) is programmed so that the desired pro-
gram memory page is addressed. If a return from a
CALL
instruction (or interrupt) is executed, the entire
13-bit PC is PUSHed onto the stack. Therefore, manip-
ulation of the PCLATH<3> is not required for the return
instructions (which POPs the address from the stack).
Note 1:
There are no status bits to indicate stack
overflow or stack underflow conditions.
Note 2:
There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW,
and
RETFIE
instructions, or the vectoring to an inter-
rupt address.
Note 1:
The PIC16C710/71/711/72 ignore both
paging bits (PCLATH<4:3>, which are
used to access program memory when
more than one page is available. The use
of PCLATH<4:3> as general purpose
read/write bits for the PIC16C7X is not
recommended since this may affect
upward compatibility with future products.
The PIC16C73/73A/74/74A ignores pag-
ing bit (PCLATH<4>), which is used to
access program memory pages 2 and 3
(1000h - 1FFFh). The use of PCLATH<4>
as a general purpose read/write bit is not
recommended since this may affect
upward compatibility with future products.