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參數(shù)資料
| 型號(hào)： | PIC16CE623T-30/SO |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 28/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 512X14 EE COMP 18SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,100 |
| 系列： | PIC® 16C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 30MHz |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲(chǔ)器容量： | 896B（512 x 14） |
| 程序存儲(chǔ)器類型： | OTP |
| EEPROM 大?。?/td> | 128 x 8 |
| RAM 容量： | 96 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 18-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | PIC16CE623T30/SO |
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1999 Microchip Technology Inc.
DS40182C-page 23
PIC16CE62X
5.0
I/O PORTS
The PIC16CE62X parts have two ports, PORTA and
PORTB. Some pins for these I/O ports are multiplexed
with an alternate function for the peripheral features on
the device. In general, when a peripheral is enabled,
that pin may not be used as a general purpose I/O pin.
5.1
PORTA and TRISA Registers
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input
and an open drain output. Port RA4 is multiplexed with the
T0CKI clock input. All other RA port pins have Schmitt
Trigger input levels and full CMOS output drivers. All pins
have data direction bits (TRIS registers), which can con-
figure these pins as input or output.
A ’1’ in the TRISA register puts the corresponding output
driver in a hi- impedance mode. A ’0’ in the TRISA register
puts the contents of the output latch on the selected pin(s).
Reading the PORTA register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch.
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(Comparator
Control
Register)
register
and
the
VRCON (Voltage Reference Control Register) register.
When selected as a comparator input, these pins will
read as ’0’s.
FIGURE 5-1:
BLOCK DIAGRAM OF
RA<1:0> PINS
Data
Bus
Q
D
Q
CK
P
N
WR
PortA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Analog
VSS
VDD
I/O Pin
Q
D
Q
CK
Input Mode
D
Q
EN
To Comparator
Schmitt Trigger
Input Buffer
VDD
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the VREF pin is a
very high impedance output. The user must configure
TRISA<2> bit as an input and use high impedance
loads.
In one of the comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA<4:3> bits must be
cleared to enable outputs to use this function.
EXAMPLE 5-1:
INITIALIZING PORTA
FIGURE 5-2:
BLOCK DIAGRAM OF RA2 PIN
Note:
On reset, the TRISA register is set to all
inputs. The digital inputs are disabled and
the comparator inputs are forced to ground
to reduce excess current consumption.
CLRF
PORTA
;Initialize PORTA by setting
;output data latches
MOVLW 0X07
;Turn comparators off and
MOVWF CMCON
;enable pins for I/O
;functions
BSF
STATUS, RP0 ;Select Bank1
MOVLW 0x1F
;Value used to initialize
;data direction
MOVWF TRISA
;Set RA<4:0> as inputs
;TRISA<7:5> are always
;read as ’0’.
Data
Bus
Q
D
Q
CK
P
N
WR
PortA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Analog
VSS
VDD
RA2 Pin
Q
D
Q
CK
Input Mode
D
Q
EN
To Comparator
Schmitt Trigger
Input Buffer
VROE
VREF
VDD
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