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參數(shù)資料
| 型號： | PIC16CE623T-30/SO |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 72/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 512X14 EE COMP 18SOIC |
| 標準包裝： | 1,100 |
| 系列： | PIC® 16C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 30MHz |
| 外圍設備： | 欠壓檢測/復位，POR，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲器容量： | 896B（512 x 14） |
| 程序存儲器類型： | OTP |
| EEPROM 大?。?/td> | 128 x 8 |
| RAM 容量： | 96 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 18-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | PIC16CE623T30/SO |
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1999 Microchip Technology Inc.
DS40182C-page 63
PIC16CE62X
10.8
Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set and the oscillator driver is
turned off. The I/O ports maintain the status they had
before SLEEP was executed (driving high, low, or
hi-impedance).
For lowest current consumption in this mode, all I/O
pins should be either at VDD or VSS, with no external
circuitry drawing current from the I/O pin, and the com-
parators and VREF should be disabled. I/O pins that are
hi-impedance inputs should be pulled high or low exter-
nally to avoid switching currents caused by floating
inputs. The T0CKI input should also be at VDD or VSS
for lowest current consumption. The contribution from
on chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
10.8.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
External reset input on MCLR pin
2.
Watchdog Timer Wake-up (if WDT was enabled)
3.
Interrupt from RB0/INT pin, RB Port change, or
the Peripheral Interrupt (Comparator).
The first event will cause a device reset. The two latter
events are considered a continuation of program exe-
cution. The TO and PD bits in the STATUS register can
be used to determine the cause of device reset.
PD
bit, which is set on power-up is cleared when SLEEP is
invoked. TO bit is cleared if WDT wake-up occurred.
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have an NOP after the SLEEP instruction.
The WDT is cleared when the device wakes-up from
sleep, regardless of the source of wake-up.
Note:
It should be noted that a RESET generated
by a WDT time-out does not drive MCLR
pin low.
Note:
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from sleep. The
sleep instruction is completely executed.
FIGURE 10-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1
Q2
Q3 Q4
Q1 Q2
Q3
Q4
Q1
Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1
Q2 Q3
Q4
Q1 Q2
Q3
Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC
PC+1
PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h)
Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2
0004h
0005h
Dummy cycle
TOST(2)
PC+2
Note 1:
XT, HS or LP oscillator mode assumed.
2:
TOST = 1024TOSC (drawing not to scale) This delay does not occur for RC osc mode.
3:
GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
4:
CLKOUT is not available in these osc modes, but shown here for timing reference.
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