參數(shù)資料
型號： PIC16CE623T-30/SO
廠商： Microchip Technology
文件頁數(shù)： 55/100頁
文件大?。?/td> 0K
描述： IC MCU OTP 512X14 EE COMP 18SOIC
標準包裝： 1,100
系列： PIC® 16C
核心處理器： PIC
芯體尺寸： 8-位
速度： 30MHz
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，WDT
輸入/輸出數(shù)： 13
程序存儲器容量： 896B（512 x 14）
程序存儲器類型： OTP
EEPROM 大小： 128 x 8
RAM 容量： 96 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 18-SOIC（0.295"，7.50mm 寬）
包裝： 帶卷 (TR)
其它名稱： PIC16CE623T30/SO
PIC16CE62X
DS40182C-page 48
1999 Microchip Technology Inc.
EXAMPLE 9-1:
VOLTAGE REFERENCE
CONFIGURATION
9.2
Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 9-1) keep VREF from approaching VSS or VDD.
The Voltage Reference is VDD derived and therefore,
the VREF output changes with fluctuations in VDD. The
absolute accuracy of the Voltage Reference can be
found in Table 13-2.
9.3
Operation During Sleep
When the device wakes up from sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the Voltage
Reference should be disabled.
MOVLW
0x02
; 4 Inputs Muxed
MOVWF
CMCON
; to 2 comps.
BSF
STATUS,RP0
; go to Bank 1
MOVLW
0x07
; RA3-RA0 are
MOVWF
TRISA
; outputs
MOVLW
0xA6
; enable VREF
MOVWF
VRCON
; low range
; set VR<3:0>=6
BCF
STATUS,RP0
; go to Bank 0
CALL
DELAY10
; 10
s delay
9.4
Effects of a Reset
A device reset disables the Voltage Reference by clear-
ing bit VREN (VRCON<7>). This reset also disconnects
the reference from the RA2 pin by clearing bit VROE
(VRCON<6>) and selects the high voltage range by
clearing bit VRR (VRCON<5>). The VREF value select
bits, VRCON<3:0>, are also cleared.
9.5
Connection Considerations
The
Voltage
Reference
Module
operates
independently of the comparator module. The output of
the reference generator may be connected to the RA2
pin if the TRISA<2> bit is set and the VROE bit,
VRCON<6>, is set. Enabling the Voltage Reference
output onto the RA2 pin with an input signal present will
increase current consumption. Connecting RA2 as a
digital
output with VREF enabled will also increase
current consumption.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
Voltage Reference output for external connections to
VREF.
shows
an
example
buffering
technique.
FIGURE 9-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
TABLE 9-1:
REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Legend: - = Unimplemented, read as "0"
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value On
POR / BOD
Value On
All Other
Resets
9Fh
VRCON
VREN
VROE
VRR
—VR3
VR2
VR1
VR0
000- 0000
1Fh
CMCON
C2OUT
C1OUT
—
CIS
CM2
CM1
CM0
00-- 0000
85h
TRISA
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111
VREF Output
+
–
VREF
Module
Voltage
Reference
Output
Impedance
R
(1)
RA2
Note 1:
R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.
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