參數(shù)資料
型號(hào): PIC16CR77-I/ML
廠商: Microchip Technology
文件頁數(shù): 29/172頁
文件大?。?/td> 0K
描述: IC PIC MCU 8KX14 44QFN
標(biāo)準(zhǔn)包裝: 45
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲(chǔ)器容量: 14KB(8K x 14)
程序存儲(chǔ)器類型: ROM
RAM 容量: 368 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VQFN 裸露焊盤
包裝: 管件
PIC18F2220/2320/4220/4320
DS39599G-page 122
2007 Microchip Technology Inc.
12.1
Timer1 Operation
Timer1 can operate in one of these modes:
As a timer
As a synchronous counter
As an asynchronous counter
The operating mode is determined by the Clock Select
bit, TMR1CS (T1CON<1>).
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input, or the
Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. The TRISC1:TRISC0 values are
ignored and the pins read as ‘0’.
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
T1OSC
TMR1H
TMR1L
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Peripheral Clocks
FOSC/4
Internal
Clock
TMR1ON
On/Off
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
1
Synchronized
Clock Input
2
TMR1IF
Overflow
TMR1
CLR
CCP Special Event Trigger
T1OSCEN
Enable
Oscillator(1)
Interrupt
Flag bit
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T1OSI
T1CKI/T1OSO
Timer 1
TMR1L
T1OSC
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Peripheral Clocks
T1OSCEN
Enable
Oscillator(1)
TMR1IF
Overflow
Interrupt
FOSC/4
Internal
Clock
TMR1ON
on/off
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
1
Synchronized
Clock Input
2
T1CKI/T1OSO
T1OSI
TMR1
Flag bit
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
High Byte
Data Bus<7:0>
8
TMR1H
8
Read TMR1L
Write TMR1L
CLR
CCP Special Event Trigger
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