參數(shù)資料
型號(hào): PIC16F526-I/SL
廠(chǎng)商: Microchip Technology
文件頁(yè)數(shù): 115/122頁(yè)
文件大小: 0K
描述: IC PIC MCU FLASH 1KX12 14SOIC
產(chǎn)品培訓(xùn)模塊: 8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 57
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 11
程序存儲(chǔ)器容量: 1.5KB(1K x 12)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 67 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 638 (CN2011-ZH PDF)
配用: ICE2000-ND - EMULATOR MPLAB-ICE 2000 POD
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PIC18F2221/2321/4221/4321 FAMILY
DS39689F-page 92
2009 Microchip Technology Inc.
8.5
Operation During Code-Protect
Data EEPROM memory has its own code-protect bits in
Configuration
Words.
External
read
and
write
operations are disabled if code protection is enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect Configuration bit. Refer to Section 24.0
information.
8.6
Protection Against Spurious Write
To protect against spurious EEPROM writes, various
mechanisms have been implemented. On power-up,
the WREN bit is cleared. In addition, writes to the
EEPROM are blocked during the Power-up Timer
period (TPWRT, parameter 33).
The write initiate sequence and the WREN bit together
help prevent an accidental write during Brown-out
Reset, power glitch or software malfunction.
8.7
Using the Data EEPROM
The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing data. Such data is
typically updated at least one time within the number of
writes defined by specification, D124. If any location
storing data is not written at least this often, the data
EEPROM array must be refreshed. For this reason,
values that change infrequently, or not at all, should be
stored in Flash program memory.
A simple data EEPROM refresh routine is shown in
EXAMPLE 8-3:
DATA EEPROM REFRESH ROUTINE
Note:
If data EEPROM is only used to store con-
stants and/or data that changes often, an
array refresh is likely not required. See
specification, D124.
CLRF
EEADR
; Start at address 0
BCF
EECON1, CFGS
; Set for memory
BCF
EECON1, EEPGD
; Set for Data EEPROM
BCF
INTCON, GIE
; Disable interrupts
BSF
EECON1, WREN
; Enable writes
LOOP
; Loop to refresh array
BSF
EECON1, RD
; Read current address
MOVLW
55h
;
MOVWF
EECON2
; Write 55h
MOVLW
0AAh
;
MOVWF
EECON2
; Write 0AAh
BSF
EECON1, WR
; Set WR bit to begin write
BTFSC
EECON1, WR
; Wait for write to complete
BRA
$-2
INCFSZ
EEADR, F
; Increment address
BRA
LOOP
; Not zero, do it again
BCF
EECON1, WREN
; Disable writes
BSF
INTCON, GIE
; Enable interrupts
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