參數(shù)資料
型號(hào): PIC16F526-I/SL
廠商: Microchip Technology
文件頁數(shù): 22/122頁
文件大小: 0K
描述: IC PIC MCU FLASH 1KX12 14SOIC
產(chǎn)品培訓(xùn)模塊: 8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 57
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 11
程序存儲(chǔ)器容量: 1.5KB(1K x 12)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 67 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 638 (CN2011-ZH PDF)
配用: ICE2000-ND - EMULATOR MPLAB-ICE 2000 POD
PIC18F2221/2321/4221/4321 FAMILY
DS39689F-page 118
2009 Microchip Technology Inc.
TABLE 11-5:
PORTC I/O SUMMARY
Pin
Function
TRIS
Setting
I/O
Type
Description
RC0/T1OSO/
T13CKI
RC0
0
O
DIG
LATC<0> data output.
1
I
ST
PORTC<0> data input.
T1OSO
x
O
ANA
Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
T13CKI
1
I
ST
Timer1/Timer3 counter input.
RC1/T1OSI/CCP2
RC1
0
O
DIG
LATC<1> data output.
1
I
ST
PORTC<1> data input.
T1OSI
x
I
ANA
Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
CCP2(1)
0
O
DIG
CCP2 compare and PWM output; takes priority over port data.
1
I
ST
CCP2 capture input.
RC2/CCP1/P1A
RC2
0
O
DIG
LATC<2> data output.
1
I
ST
PORTC<2> data input.
CCP1
0
O
DIG
CCP1 compare or PWM output; takes priority over port data.
1
I
ST
CCP1 capture input.
P1A(2)
0
O
DIG
ECCP1 Enhanced PWM output, Channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
RC3/SCK/SCL
RC3
0
O
DIG
LATC<3> data output.
1
I
ST
PORTC<3> data input.
SCK
0
O
DIG
SPI clock output (MSSP module); takes priority over port data.
1
I
ST
SPI clock input (MSSP module).
SCL
0
ODIG
I2C clock output (MSSP module); takes priority over port data.
1
II2C/SMB I2C clock input (MSSP module); input type depends on module setting.
RC4/SDI/SDA
RC4
0
O
DIG
LATC<4> data output.
1
I
ST
PORTC<4> data input.
SDI
1
I
ST
SPI data input (MSSP module).
SDA
1
ODIG
I2C data output (MSSP module); takes priority over port data.
1
II2C/SMB I2C data input (MSSP module); input type depends on module setting.
RC5/SDO
RC5
0
O
DIG
LATC<5> data output.
1
I
ST
PORTC<5> data input.
SDO
0
O
DIG
SPI data output (MSSP module); takes priority over port data.
RC6/TX/CK
RC6
0
O
DIG
LATC<6> data output.
1
I
ST
PORTC<6> data input.
TX
1
O
DIG
Asynchronous serial transmit data output (EUSART module);
takes priority over port data. User must configure as output.
CK
1
O
DIG
Synchronous serial clock output (EUSART module); takes priority
over port data.
1
I
ST
Synchronous serial clock input (EUSART module).
RC7/RX/DT
RC7
0
O
DIG
LATC<7> data output.
1
I
ST
PORTC<7> data input.
RX
1
I
ST
Asynchronous serial receive data input (EUSART module).
DT
1
O
DIG
Synchronous serial data output (EUSART module); takes priority over
port data.
1
I
ST
Synchronous serial data input (EUSART module). User must
configure as an input.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1:
Default assignment for CCP2 when the CCP2MX Configuration bit is set. Alternate assignment is RB3.
2:
Enhanced PWM output is available only on PIC18F4221/4321 devices.
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