參數(shù)資料
型號: PIC18F2331-I/SO
廠商: Microchip Technology
文件頁數(shù): 113/119頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 4KX16 28SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 27
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,電源控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 24
程序存儲器容量: 8KB(4K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 645 (CN2011-ZH PDF)
配用: XLT28SO-1-ND - SOCKET TRANSITION 28SOIC 300MIL
I3-DB18F4431-ND - BOARD DAUGHTER ICEPIC3
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
93
M9999-100207-1.5
Bit
Default
R/W
Description
Is the same as:
11
0
RW
Power down
1 = power down
0 = normal operation
P2MBCR, bit 11
10
0
RW
Disable auto MDI/MDIX
1 = disable auto MDI/MDIX function
0 = enable auto MDI/MDIX function
P2MBCR, bit 3
9
0
RW
Force MDIX
1 = If auto MDI/MDIX is disabled, force PHY into
MDIX mode
0 = Do not force PHY into MDIX mode
P2MBCR, bit 4
8
0
RW
Loop back
1 = perform loop back, as indicated:
Start: RXP1/RXM1 (port 1)
Loop back: PMD/PMA of port 2’s PHY
End: TXP1/TXM1 (port 1)
0 = normal operation
P2MBCR, bit 14
7
1
RW
Auto Negotiation Enable
0 = disable auto negotiation, speed and duplex are
decided by bit 6 and 5 of the same register.
1 = auto negotiation is ON
P2MBCR, bit 12
6
0
RW
Force Speed
1 = force 100Base-T if AN is disabled (bit 7)
0 = force 10Base-T if AN is disabled (bit 7)
P2MBCR, bit 13
5
0
RW
Force duplex
1 = force full duplex if (1) AN is disabled or (2) AN is
enabled but failed.
0 = force half duplex if (1) AN is disabled or (2) AN is
enabled but failed.
P2MBCR, bit 9
4
1
RW
Advertised flow control capability
1 = advertise flow control (pause) capability
0 = suppress flow control (pause) capability from
transmission to link partner
P1ANAR, bit 4
3
1
RW
Advertised 100BT Full duplex capability
1 = advertise 100Base-T Full duplex capability
0 = suppress 100Base-T Full duplex capability from
transmission to link partner
P1ANAR, bit 3
2
1
RW
Advertised 100BT half duplex capability
1 = advertise 100Base-T Half duplex capability
0 = suppress 100Base-T Half duplex capability from
transmission to link partner
P1ANAR, bit 2
1
RW
Advertised 10BT Full duplex capability
1 = advertise 10Base-T Full duplex capability
0 = suppress 10Base-T Full duplex capability from
transmission to link partner
P1ANAR, bit 1
0
1
RW
Advertised 10BT half duplex capability
1 = advertise 10Base-T Half duplex capability
0 = suppress 10Base-T Half duplex capability from
transmission to link partner
P1ANAR, bit 0
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