參數(shù)資料
型號: PIC18F2331-I/SO
廠商: Microchip Technology
文件頁數(shù): 75/119頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 4KX16 28SOIC
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 27
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,LVD,電源控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 24
程序存儲器容量: 8KB(4K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 645 (CN2011-ZH PDF)
配用: XLT28SO-1-ND - SOCKET TRANSITION 28SOIC 300MIL
I3-DB18F4431-ND - BOARD DAUGHTER ICEPIC3
2010 Microchip Technology Inc.
DS39616D-page 59
PIC18F2331/2431/4331/4431
CAP3BUFL/
MAXCNTL
2331 2431 4331 4431
xxxx xxxx
uuuu uuuu
CAP1CON
2331 2431 4331 4431
-0-- 0000
-u-- uuuu
CAP2CON
2331 2431 4331 4431
-0-- 0000
-u-- uuuu
CAP3CON
2331 2431 4331 4431
-0-- 0000
-u-- uuuu
DFLTCON
2331 2431 4331 4431
-000 0000
-uuu uuuu
TABLE 5-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET
Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u
= unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1:
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4:
See Table 5-2 for Reset value for specific condition.
5:
Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6:
Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE
pin, they are disabled and read as ‘0’. The 28-pin devices do not have only RE3 implemented.
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