I2
參數(shù)資料
型號： PIC18F2520-I/SP
廠商： Microchip Technology
文件頁數(shù)： 33/151頁
文件大?。?/td> 0K
描述： IC MCU FLASH 16KX16 28-DIP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 15
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，HLVD，POR，PWM，WDT
輸入/輸出數(shù)： 25
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量： 1.5K x 8
電壓 - 電源 (Vcc/Vdd)： 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-DIP（0.300"，7.62mm）
包裝： 管件
產(chǎn)品目錄頁面： 643 (CN2011-ZH PDF)
配用： MCP3909RD-3PH1-ND - REF DESIGN MCP3909 3PH ENGY MTR
DVA18XP280-ND - DEVICE ADAPTER 18F2220 PDIP 28LD
PIC16(L)F1782/3
DS41579C-page 300
Preliminary
2011-2012 Microchip Technology Inc.
26.6.6
I2C MASTER MODE TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted. SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high. When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received prop-
erly. The status of ACK is written into the ACKSTAT bit
on the rising edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 26-27).
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
release the SDA pin, allowing the slave to respond with
an Acknowledge. On the falling edge of the ninth clock,
the master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT Status bit of the SSPCON2
register. Following the falling edge of the ninth clock
transmission of the address, the SSPIF is set, the BF
flag is cleared and the Baud Rate Generator is turned
off until another write to the SSPBUF takes place, hold-
ing SCL low and allowing SDA to float.
26.6.6.1
BF Status Flag
In Transmit mode, the BF bit of the SSPSTAT register
is set when the CPU writes to SSPBUF and is cleared
when all 8 bits are shifted out.
26.6.6.2
WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the buf-
fer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.
26.6.6.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit of the SSPCON2
register is cleared when the slave has sent an Acknowl-
edge (ACK = 0) and is set when the slave does not
Acknowledge (ACK = 1). A slave sends an Acknowl-
edge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
26.6.6.4
Typical transmit sequence:
1.
The user generates a Start condition by setting
the SEN bit of the SSPCON2 register.
2.
SSPIF is set by hardware on completion of the
Start.
3.
SSPIF is cleared by software.
4.
The MSSP module will wait the required start
time before any other operation takes place.
5.
The user loads the SSPBUF with the slave
address to transmit.
6.
Address is shifted out the SDA pin until all 8 bits
are transmitted. Transmission begins as soon
as SSPBUF is written to.
7.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
8.
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
9.
The user loads the SSPBUF with eight bits of
data.
10. Data is shifted out the SDA pin until all 8 bits are
transmitted.
11. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
12. Steps 8-11 are repeated for all transmitted data
bytes.
13. The user generates a Stop or Restart condition
by setting the PEN or RSEN bits of the
SSPCON2 register. Interrupt is generated once
the Stop/Restart condition is complete.
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PIC18F2520T-E/SO 功能描述:8位微控制器 -MCU 32KB Flash 1536RAM 23I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC18F2520T-I/ML 功能描述:8位微控制器 -MCU 32KB 3968 RAM 25I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC18F2520T-I/SO 功能描述:8位微控制器 -MCU 32KB 3968 RAM 25I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC18F2523-E/ML 功能描述:8位微控制器 -MCU 32KB FL 1536bytes- RAM 25I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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