參數(shù)資料
型號(hào): PIC18F2520-I/SP
廠商: Microchip Technology
文件頁數(shù): 57/151頁
文件大?。?/td> 0K
描述: IC MCU FLASH 16KX16 28-DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 15
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 25
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 1.5K x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 643 (CN2011-ZH PDF)
配用: MCP3909RD-3PH1-ND - REF DESIGN MCP3909 3PH ENGY MTR
DVA18XP280-ND - DEVICE ADAPTER 18F2220 PDIP 28LD
PIC16(L)F1782/3
DS41579C-page 324
Preliminary
2011-2012 Microchip Technology Inc.
27.1.2.8
Asynchronous Reception Set-up:
1.
Initialize the SPBRGH, SPBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 27.4 “EUSART
2.
Clear the ANSEL bit for the RX pin (if applicable).
3.
Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4.
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5.
If 9-bit reception is desired, set the RX9 bit.
6.
Enable reception by setting the CREN bit.
7.
The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
8.
Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
9.
Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
27.1.2.9
9-bit Address Detection Mode Set-up
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
Initialize the SPBRGH, SPBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 27.4 “EUSART
2.
Clear the ANSEL bit for the RX pin (if applicable).
3.
Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4.
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5.
Enable 9-bit reception by setting the RX9 bit.
6.
Enable address detection by setting the ADDEN
bit.
7.
Enable reception by setting the CREN bit.
8.
The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCIE interrupt enable bit
was also set.
9.
Read the RCSTA register to get the error flags.
The ninth data bit will always be set.
10. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 27-5:
ASYNCHRONOUS RECEPTION
Start
bit
bit 7/8
bit 1
bit 0
bit 7/8
bit 0
Stop
bit
Start
bit
Start
bit
bit 7/8 Stop
bit
RX/DT pin
Reg
Rcv Buffer Reg.
Rcv Shift
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
Stop
bit
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
RCIDL
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