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參數(shù)資料
型號: PIC18F2520-I/SP
廠商: Microchip Technology
文件頁數(shù): 86/151頁
文件大小: 0K
描述: IC MCU FLASH 16KX16 28-DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 15
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 25
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 256 x 8
RAM 容量: 1.5K x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 643 (CN2011-ZH PDF)
配用: MCP3909RD-3PH1-ND - REF DESIGN MCP3909 3PH ENGY MTR
DVA18XP280-ND - DEVICE ADAPTER 18F2220 PDIP 28LD
2011-2012 Microchip Technology Inc.
Preliminary
DS41579C-page 353
PIC16(L)F1782/3
29.2
Instruction Descriptions
ADDFSR
Add Literal to FSRn
Syntax:
[ label ] ADDFSR FSRn, k
Operands:
-32
k 31
n
[ 0, 1]
Operation:
FSR(n) + k
FSR(n)
Status Affected:
None
Description:
The signed 6-bit literal ‘k’ is added to
the contents of the FSRnH:FSRnL
register pair.
FSRn is limited to the range 0000h -
FFFFh. Moving beyond these bounds
will cause the FSR to wrap-around.
ADDLW
Add literal and W
Syntax:
[ label ] ADDLW
k
Operands:
0
k 255
Operation:
(W) + k
(W)
Status Affected:
C, DC, Z
Description:
The contents of the W register are
added to the eight-bit literal ‘k’ and the
result is placed in the W register.
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
f,d
Operands:
0
f 127
d
0,1
Operation:
(W) + (f)
(destination)
Status Affected:
C, DC, Z
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
ADDWFC
ADD W and CARRY bit to f
Syntax:
[ label ] ADDWFC
f {,d}
Operands:
0
f 127
d
[0,1]
Operation:
(W) + (f) + (C)
dest
Status Affected:
C, DC, Z
Description:
Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
ANDLW
AND literal with W
Syntax:
[ label ] ANDLW
k
Operands:
0
k 255
Operation:
(W) .AND. (k)
(W)
Status Affected:
Z
Description:
The contents of W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W register.
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
f,d
Operands:
0
f 127
d
0,1
Operation:
(W) .AND. (f)
(destination)
Status Affected:
Z
Description:
AND the W register with register ‘f’. If
‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
ASRF
Arithmetic Right Shift
Syntax:
[ label ] ASRF
f {,d}
Operands:
0
f 127
d
[0,1]
Operation:
(f<7>)
dest<7>
(f<7:1>)
dest<6:0>,
(f<0>)
C,
Status Affected:
C, Z
Description:
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in reg-
ister ‘f’.
register f
C
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