TR MCLR Rise Time to Enter" />
參數(shù)資料
型號: PIC18F26J50-I/SP
廠商: Microchip Technology
文件頁數(shù): 24/32頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 64K 2V 28-DIP
產(chǎn)品培訓模塊: XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標準包裝: 15
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設備: 欠壓檢測/復位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2.15 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 657 (CN2011-ZH PDF)
配用: AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
PIC18F2XJXX/4XJXX FAMILY
DS39687E-page 30
2009 Microchip Technology Inc.
P1
TR
MCLR Rise Time to Enter Program/Verify
mode
—1.0
μs
P2
TPGC
Serial Clock (PGC) Period
100
ns
P2A
TPGCL
Serial Clock (PGC) Low Time
50
ns
P2B
TPGCH
Serial Clock (PGC) High Time
50
ns
P3
TSET1
Input Data Setup Time to Serial Clock
20
ns
P4
THLD1
Input Data Hold Time from PGC
20
ns
P5
TDLY1
Delay Between 4-Bit Command and
Command Operand
50
ns
P5A
TDLY1A
Delay Between 4-Bit Command Operand and
Next 4-Bit Command
50
ns
P6
TDLY2
Delay Between Last PGC
↓ of Command Byte
to First PGC
↑ of Read of Data Word
20
ns
P9
TDLY5
Delay to allow Block Programming to Occur
3.4
ms
PIC18F2XJ10/PIC18F4XJ10
1.2
ms
PIC18F2XJ11/PIC18F4XJ11/
PIC18F2XJ13/PIC18F4XJ13/
PIC18F2XJ5X/PIC18F4XJ5X
P10
TDLY6
Delay to allow Row Erase to Occur
49
ms
PIC18F2XJ10/PIC18F4XJ10/
PIC18F2XJ13/PIC18F4XJ13/
PIC18F2XJ53/PIC18F4XJ53
54
ms
PIC18F2XJ11/PIC18F4XJ11/
PIC18F2XJ50/PIC18F4XJ50
P11
TDLY7
Delay to allow Bulk Erase to Occur
475
ms
PIC18F2XJ10/PIC18F4XJ10/
PIC18F2XJ13/PIC18F4XJ13/
PIC18F2XJ53/PIC18F4XJ53
524
ms
PIC18F2XJ11/PIC18F4XJ11/
PIC18F2XJ50/PIC18F4XJ50
P12
THLD2
Input Data Hold Time from MCLR
400
μs
P13
TSET2VDD
↑ Setup Time to MCLR ↑
100
ns
P14
TVALID
Data Out Valid from PGC
25
ns
P16
TDLY8
Delay Between Last PGC
↓ and MCLR ↓
20
ns
P17
THLD3MCLR
↓ to VDD
3—
μs
P19
TKEY1
Delay from First MCLR
↓ to First PGC ↑ for
Key Sequence on PGD
4—
ms
P20
TKEY2
Delay from Last PGC
↓ for Key Sequence on
PGD to Second MCLR
50
ns
6.0
AC/DC CHARACTERISTICS TIMING REQUIREMENTS
FOR PROGRAM/VERIFY TEST MODE (CONTINUED)
Standard Operating Conditions
Operating Temperature: 25
°C is recommended
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
Note 1:
External power must be supplied to the VDDCORE/VCAP pin if the on-chip voltage regulator is disabled. See
Section 2.1.1 “PIC18F2XJXX/4XJXX/ LF2XJXX/LF4XJXX Devices and the On-Chip Voltage Regulator” for
more information.
2:
VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within ±0.3V
of VDD and VSS, respectively.
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