參數(shù)資料
型號: PIC18F26J50-I/SP
廠商: Microchip Technology
文件頁數(shù): 32/32頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 64K 2V 28-DIP
產(chǎn)品培訓(xùn)模塊: XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 15
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2.15 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 657 (CN2011-ZH PDF)
配用: AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
2009 Microchip Technology Inc.
DS39687E-page 9
PIC18F2XJXX/4XJXX FAMILY
3.0
DEVICE PROGRAMMING
Programming includes the ability to erase or write the
memory within the device.
The EECON1 register is used to control Write or Row
Erase operations. The WREN bit must be set to enable
writes; this must be done prior to initiating a write
sequence. It is strongly recommended that the WREN
bit only be set immediately prior to a program or erase
operation.
The FREE bit must be set in order to erase the program
space being pointed to by the Table Pointer. The erase
or write sequence is initiated by setting the WR bit.
3.1
ICSP Erase
3.1.1
ICSP BULK ERASE
Devices of the PIC18F2XJXX/4XJXX family may be
Bulk Erased by writing 0180h to the table address,
3C0005h:3C0004h. The basic sequence is shown in
Table 3-1 and demonstrated in Figure 3-1.
Since the code-protect Configuration bit is stored in the
program code within code memory, a Bulk Erase
operation will also clear any code-protect settings for
the device.
The actual Bulk Erase function is a self-timed opera-
tion. Once the erase has started (falling edge of the 4th
PGC after the NOP command), serial execution will
cease until the erase completes (parameter P11).
During this time, PGC may continue to toggle but PGD
must be held low.
TABLE 3-1:
BULK ERASE COMMAND
SEQUENCE
FIGURE 3-1:
BULK ERASE FLOW
FIGURE 3-2:
BULK ERASE TIMING
4-Bit
Command
Data
Payload
Core Instruction
0000
1100
0000
1100
0000
0E 3C
6E F8
0E 00
6E F7
0E 05
6E F6
01 01
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
80 80
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 05h
MOVWF TBLPTRL
Write 01h to 3C0005h
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 80h TO 3C0004h to
erase entire device.
NOP
Hold PGD low until erase
completes.
Start
Done
Write 8080h to
3C0004h to Erase
Entire Device
Write 0101h
Delay P11 + P10
Time
to 3C0005h
n
12
3
4
1
215 16
12
3
PGC
P5
P5A
PGD
PGD = Input
0
00
1
P11
P10
Erase Time
00
0
12
00
4
0
1
2
15 16
P5
12
3
P5A
4
000
0
n
4-Bit Command
16-Bit
Data Payload
16-Bit
Data Payload
16-Bit
Data Payload
11
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