參數(shù)資料
型號： PIC18F45J50-I/ML
廠商： Microchip Technology
文件頁數(shù)： 12/164頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 32K 2V 44-QFN
產(chǎn)品培訓(xùn)模塊： XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 45
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 48MHz
連通性： I²C，SPI，UART/USART，USB
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 3.8K x 8
電壓 - 電源 (Vcc/Vdd)： 2.15 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-VQFN 裸露焊盤
包裝： 管件
產(chǎn)品目錄頁面： 657 (CN2011-ZH PDF)
配用： AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
2011 Microchip Technology Inc.
DS39931D-page 109
PIC18F46J50 FAMILY
7.5
Writing to Flash Program Memory
The programming block is 32 words or 64 bytes.
Programming one word or 2 bytes at a time is also
supported.
Table writes are used internally to load the holding reg-
isters needed to program the Flash memory. There are
64 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte, the
TBLWT
instruction may need to be executed 64 times for
each programming operation (if WPROG = 0). All of the
table write operations will essentially be short writes
because only the holding registers are written. At the
end of updating the 64 holding registers, the EECON1
register must be written to in order to start the
programming operation with a long write.
The long write is necessary for programming the
internal Flash. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer.
The on-chip timer controls the write time. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
FIGURE 7-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
7.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1.
Read 1024 bytes into RAM.
2.
Update data values in RAM as necessary.
3.
Load the Table Pointer register with the address
being erased.
4.
Execute the erase procedure.
5.
Load the Table Pointer register with the address
of the first byte being written, minus 1.
6.
Write the 64 bytes into the holding registers with
auto-increment.
7.
Set the WREN bit (EECON1<2>) to enable byte
writes.
8.
Disable interrupts.
9.
Write 0x55 to EECON2.
10. Write 0xAA to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for the duration of the write for
TIW (see Parameter D133A).
13. Re-enable interrupts.
14. Repeat Steps 6 through 13 until all 1024 bytes
are written to program memory.
15. Verify the memory (table read).
An example of the required code is provided in
Example 7-3 on the following page.
Note 1:
Unlike previous PIC devices, devices of
the PIC18F46J50 family do not reset the
holding registers after a write occurs. The
holding registers must be cleared or
overwritten before a
programming
sequence.
2:
To maintain the endurance of the pro-
gram memory cells, each Flash byte
should not be programmed more than
once between erase operations. Before
attempting to modify the contents of the
target cell a second time, an erase of the
target page, or a bulk erase of the entire
memory, must be performed.
TABLAT
TBLPTR = xxxx3F
TBLPTR = xxxxx1
TBLPTR = xxxxx0
Write Register
TBLPTR = xxxxx2
Program Memory
Holding Register
8
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
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