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參數(shù)資料
| 型號： | PIC18F45J50-I/ML |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 127/164頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 32K 2V 44-QFN |
| 產(chǎn)品培訓模塊： | XLP Deep Sleep Mode PIC18 J Series MCU Overview 8-bit PIC® Microcontroller Portfolio |
| 標準包裝： | 45 |
| 系列： | PIC® XLP™ 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 48MHz |
| 連通性： | I²C，SPI，UART/USART，USB |
| 外圍設備： | 欠壓檢測/復位，DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 32KB（16K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 3.8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.15 V ~ 3.6 V |
| 數(shù)據(jù)轉換器： | A/D 13x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-VQFN 裸露焊盤 |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 657 (CN2011-ZH PDF) |
| 配用： | AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN |
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2011 Microchip Technology Inc.
DS39931D-page 65
PIC18F46J50 FAMILY
5.2
Master Clear (MCLR)
The Master Clear Reset (MCLR) pin provides a method
for triggering a hard external Reset of the device. A
Reset is generated by holding the pin low. PIC18
extended microcontroller devices have a noise filter in
the MCLR Reset path, which detects and ignores small
pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
5.3
Power-on Reset (POR)
A POR condition is generated on-chip whenever VDD
rises above a certain threshold. This allows the device
to start in the initialized state when VDD is adequate for
operation.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k
to 10 k) to VDD. This will
eliminate external RC components usually needed to
create a POR delay.
When the device starts normal operation (i.e., exits the
Reset
condition),
device
operating
parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a Power-on
Reset occurs; it does not change for any other Reset
event. POR is not reset to ‘1’ by any hardware event.
To capture multiple events, the user manually resets
the bit to ‘1’ in software following any POR.
5.4
Brown-out Reset (BOR)
The “F” devices in the PIC18F46J50 family incorporate
two types of BOR circuits: one which monitors
VDDCORE and one which monitors VDD. Only one BOR
circuit can be active at a time. When in normal Run
mode, Idle or normal Sleep modes, the BOR circuit that
monitors VDDCORE is active and will cause the device
to be held in BOR if VDDCORE drops below VBOR
(Parameter D005). Once VDDCORE rises back above
VBOR, the device will be held in Reset until the
expiration of the Power-up Timer, with period, TPWRT
(Parameter 33).
During Deep Sleep operation, the on-chip core voltage
regulator is disabled and VDDCORE is allowed to drop to
VSS. If the Deep Sleep BOR circuit is enabled by the
DSBOREN bit (CONFIG3L<2> = 1), it will monitor VDD.
If VDD drops below the VDSBOR threshold, the device
will be held in a Reset state similar to POR. All registers
will be set back to their Power-on Reset values and the
contents of the DSGPR0 and DSGPR1 holding regis-
ters will be lost. Additionally, if any I/O pins had been
configured as outputs during Deep Sleep, these pins
will be tri-stated and the device will no longer be held in
Deep Sleep. Once the VDD voltage recovers back
above the VDSBOR threshold, and once the core
voltage regulator achieves a VDDCORE voltage above
VBOR, the device will begin executing code again
normally, but the DS bit in the WDTCON register will
not be set. The device behavior will be similar to hard
cycling all power to the device.
On “LF” devices (ex: PIC18LF46J50), the VDDCORE
BOR circuit is always disabled because the internal
core voltage regulator is disabled. Instead of monitor-
ing VDDCORE, PIC18LF devices in this family can still
use the VDD BOR circuit to monitor VDD excursions
below the VDSBOR threshold. The VDD BOR circuit can
be disabled by setting the DSBOREN bit = 0.
The VDD BOR circuit is enabled when DSBOREN = 1
on “LF” devices, or on “F” devices while in Deep Sleep
with DSBOREN = 1. When enabled, the VDD BOR cir-
cuit is extremely low power (typ. 40nA) during normal
operation, above ~2.3V on VDD. If VDD drops below this
DSBOR arming level when the VDD BOR circuit is
enabled, the device may begin to consume additional
current (typ. 50
A) as internal features of the circuit
power-up. The higher current is necessary to achieve
more accurate sensing of the VDD level. However, the
device will not enter Reset until VDD falls below the
VDSBOR threshold.
5.4.1
DETECTING BOR
The BOR bit always resets to ‘0’ on any VDDCORE BOR
or POR event. This makes it difficult to determine if a
Brown-out Reset event has occurred just by reading
the state of BOR alone. A more reliable method is to
simultaneously check the state of both POR and BOR.
This assumes that the POR bit is reset to ‘1’ in software
immediately after any Power-on Reset event. If BOR is
‘0’ while POR is ‘1’, it can be reliably assumed that a
Brown-out Reset event has occurred.
If the voltage regulator is disabled (LF device), the
VDDCORE BOR functionality is disabled. In this case,
the BOR bit cannot be used to determine a Brown-out
Reset event. The BOR bit is still cleared by a Power-on
Reset event.
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