參數(shù)資料
型號: PIC18F87J90-I/PT
廠商: Microchip Technology
文件頁數(shù): 35/59頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 128KB 80-TQFP
產(chǎn)品培訓(xùn)模塊: PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 119
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LCD,LVD,POR,PWM,WDT
輸入/輸出數(shù): 67
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 644 (CN2011-ZH PDF)
配用: AC162079-ND - HEADER MPLAB ICD2 18F85J90 64/80
AC164323-ND - MODULE SKT FOR 100TQFP
PIC18F87J90 FAMILY
DS39933D-page 40
2010 Microchip Technology Inc.
3.4.2
EXTERNAL CLOCK INPUT
(EC MODES)
The EC and ECPLL Oscillator modes require an
external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 3-3:
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 3-4. In
this configuration, the divide-by-4 output on OSC2 is
not available. Current consumption in this configuration
will be somewhat higher than EC mode, as the internal
oscillator’s feedback circuitry will be enabled (in EC
mode, the feedback circuit is disabled).
FIGURE 3-4:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
3.4.3
PLL FREQUENCY MULTIPLIER
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator.
3.4.3.1
HSPLL and ECPLL Modes
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external
oscillating source to produce frequencies of up to
40 MHz.
The PLL is enabled by programming the FOSC<2:0>
Configuration bits to either ‘111’ (for ECPLL) or ‘101’
(for
HSPLL).
In
addition,
the
PLLEN
bit
(OSCTUNE<6>) must also be set. Clearing PLLEN
disables the PLL, regardless of the chosen oscillator
configuration. It also allows additional flexibility for
controlling the application’s clock speed in software.
FIGURE 3-5:
PLL BLOCK DIAGRAM
3.4.3.2
PLL and INTOSC
The PLL is also available to the internal oscillator block
when the internal oscillator block is configured as the
primary clock source. In this configuration, the PLL is
enabled in software and generates a clock output of up
to 32 MHz. The operation of INTOSC with the PLL is
OSC1/CLKI
OSC2/CLKO
FOSC/4
Clock from
Ext. System
PIC18F87J90
OSC1
OSC2
Open
Clock from
Ext. System
(HS Mode)
PIC18F87J90
MU
X
VCO
Loop
Filter
OSC2
OSC1
PLL Enable (OSCTUNE)
FIN
FOUT
SYSCLK
Phase
Comparator
HSPLL or ECPLL (CONFIG2L)
4
HS or EC
Mode
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