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參數(shù)資料
| 型號： | PIC18LF96J65-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 109/131頁 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 48KX16 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | PIC® 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 41.667MHz |
| 連通性： | EBI/EMI，以太網(wǎng)，I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 70 |
| 程序存儲器容量： | 96KB（48K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 3808 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 包裝： | 托盤 |
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2011 Microchip Technology Inc.
DS39762F-page 79
PIC18F97J60 FAMILY
6.1.3
PIC18F9XJ60/9XJ65 PROGRAM
MEMORY MODES
The 100-pin devices in this family can address up to a
total of 2 Mbytes of program memory. This is achieved
through the external memory bus. There are two
distinct operating modes available to the controllers:
Microcontroller (MC)
Extended Microcontroller (EMC)
The program memory mode is determined by setting
the EMB Configuration bits (CONFIG3L<5:4>), as
shown in Register 6-1. (Also see Section 25.1
for additional details on the
device Configuration bits).
The program memory modes operate as follows:
The Microcontroller Mode accesses only on-chip
Flash memory. Attempts to read above the top of
on-chip memory causes a read of all ‘0’s (a NOP
instruction).
The Microcontroller mode is also the only operating
mode available to 64-pin and 80-pin devices.
The Extended Microcontroller Mode allows
access to both internal and external program
memories as a single block. The device can
access its entire on-chip program memory. Above
this, the device accesses external program
memory up to the 2-Mbyte program space limit.
Execution automatically switches between the
two memories as required.
The setting of the EMB Configuration bits also controls
the address bus width of the external memory bus. This
is covered in more detail in Section 8.0 “External
.
In all modes, the microcontroller has complete access
to data RAM.
Figure 6-3 compares the memory maps of the different
program memory modes. The differences between
on-chip and external memory access limitations are
more fully explained in Table 6-2.
REGISTER 6-1:
CONFIG3L: CONFIGURATION REGISTER 3 LOW
R/WO-1
U-0
WAIT(1)
BW(1)
EMB1(1)
EMB0(1)
EASHFT(1)
—
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
WAIT:
External Bus Wait Enable bit(1)
1
= Wait states for operations on external memory bus are disabled
0
= Wait states for operations on external memory bus are enabled and selected by MEMCON<5:4>
bit 6
BW:
Data Bus Width Select bit(1)
1
= 16-Bit Data Width mode
0
= 8-Bit Data Width mode
bit 5-4
EMB<1:0>:
External Memory Bus Configuration bits(1)
11
= Microcontroller mode, external bus disabled
10
= Extended Microcontroller mode,12-Bit Addressing mode
01
= Extended Microcontroller mode,16-Bit Addressing mode
00
= Extended Microcontroller mode, 20-Bit Addressing mode
bit 3
EASHFT:
External Address Bus Shift Enable bit(1)
1
= Address shifting is enabled; address on external bus is offset to start at 000000h
0
= Address shifting is disabled; address on external bus reflects the PC value
bit 2-0
Unimplemented:
Read as ‘0’
Note 1:
Implemented on 100-pin devices only.
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