參數(shù)資料
型號: PK60X256VMD100
廠商: Freescale Semiconductor
文件頁數(shù): 18/79頁
文件大小: 0K
描述: IC ARM CORTEX MCU 256K 144-MAP
產(chǎn)品培訓(xùn)模塊: Kinetis® Cortex-M4 Microcontroller Family
標(biāo)準(zhǔn)包裝: 1
系列: Kinetis
核心處理器: ARM? Cortex?-M4
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,IrDA,SDHC,SPI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,I²S,LVD,POR,PWM,WDT
輸入/輸出數(shù): 100
程序存儲器容量: 256KB(256K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 33x16b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 144-LBGA
包裝: 托盤
6.1.2 JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
J1
TCLK frequency of operation
Boundary Scan
JTAG and CJTAG
Serial Wire Debug
0
10
25
50
MHz
J2
TCLK cycle period
1/J1
ns
J3
TCLK clock pulse width
Boundary Scan
JTAG and CJTAG
Serial Wire Debug
50
20
10
ns
J4
TCLK rise and fall times
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
ns
J6
Boundary scan input data hold time after TCLK rise
0
ns
J7
TCLK low to boundary scan output data valid
25
ns
J8
TCLK low to boundary scan output high-Z
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
ns
J10
TMS, TDI input data hold time after TCLK rise
1
ns
J11
TCLK low to TDO data valid
17
ns
J12
TCLK low to TDO high-Z
17
ns
J13
TRST assert time
100
ns
J14
TRST setup time (negation) to TCLK high
8
ns
Table 14. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
TCLK frequency of operation
Boundary Scan
JTAG and CJTAG
Serial Wire Debug
0
10
20
40
MHz
J2
TCLK cycle period
1/J1
ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
25
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