t
參數(shù)資料
型號: PK60X256VMD100
廠商: Freescale Semiconductor
文件頁數(shù): 46/79頁
文件大小: 0K
描述: IC ARM CORTEX MCU 256K 144-MAP
產(chǎn)品培訓模塊: Kinetis® Cortex-M4 Microcontroller Family
標準包裝: 1
系列: Kinetis
核心處理器: ARM? Cortex?-M4
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,IrDA,SDHC,SPI,UART/USART,USB,USB OTG
外圍設備: DMA,I²S,LVD,POR,PWM,WDT
輸入/輸出數(shù): 100
程序存儲器容量: 256KB(256K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 33x16b,D/A 2x12b
振蕩器型: 內部
工作溫度: -40°C ~ 105°C
封裝/外殼: 144-LBGA
包裝: 托盤
Table 31. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
80
250
600
ns
Analog comparator initialization delay2
40
μs
IDAC6b
6-bit DAC current adder (enabled)
7
μA
INL
6-bit DAC integral non-linearity
–0.5
0.5
LSB3
DNL
6-bit DAC differential non-linearity
–0.3
0.3
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.04
0.05
0.06
0.07
0.08
P
H
ys
te
re
ri
s
(V
)
00
01
10
HYSTCTR
Setting
0
0.01
0.02
0.03
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
CM
10
11
Vin level (V)
Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0)
Peripheral operating requirements and behaviors
K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
50
Freescale Semiconductor, Inc.
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