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參數(shù)資料
| 型號(hào)： | PLC18V8ZIN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | Delay On Break Timer |
| 中文描述： | OT PLD, 40 ns, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, SOT-146-1, DIP-20 |
| 文件頁數(shù)： | 14/23頁 |
| 文件大?。?/td> | 225K |
| 代理商： | PLC18V8ZIN |
Philips Semiconductors
Product specification
PLC18V8Z
Zero standby power
CMOS versatile PAL devices
1997 Aug 08
14
REGISTER PRELOAD FUNCTION
(DIAGNOSTIC MODE ONLY)
In order to facilitate the testing of state machine/controller designs, a
diagnostic mode register preload feature has been incorporated into
the PLC18V8Z series device. This feature enables the user to load
the registers with predetermined states while a super voltage is
applied to Pins 11 and 6 (I9/OE and I5). (See diagram for timing and
sequence.)
To read the data out, Pins 11 and 6 must be returned to normal TTL
levels. The outputs, F0 – F7, must be enabled in order to read data
out. The Q outputs of the registers will reflect data in as input via
F0 – F7 during preload. Subsequently, the register Q output via the
feedback path will reflect the data in as input via F0 – F7.
Refer to the voltage waveform for timing and voltage references.
t
PL
= 10
μ
sec.
REGISTER PRELOAD (DIAGNOSTIC MODE)
éééééééééééééééééééé
éééééééééééééééééééé
I
/
OE
(PIN 11)
I
5
(PIN 6)
I
/
CLK
(PIN 1)
F
0–7
I
1–4
,
6–8
PRELOAD DATA IN
PRELOAD DATA OUT
DATA OUT
OE(V
OL
)
I
0
/
CLK
F
0–7
I
1–4
,
6–8
t
PL
t
PL
t
PL
t
PL
t
PL
t
PL
t
OE
t
CKL
t
CKO
t
IS
t
IH
5.0V
5.0V
12.0V
12.0V
12.0V
5.0V
SP00022
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