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參數(shù)資料
| 型號： | PLC18V8ZIN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | Delay On Break Timer |
| 中文描述： | OT PLD, 40 ns, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, SOT-146-1, DIP-20 |
| 文件頁數(shù)： | 15/23頁 |
| 文件大?。?/td> | 225K |
| 代理商： | PLC18V8ZIN |
Philips Semiconductors
Product specification
PLC18V8Z
Zero standby power
CMOS versatile PAL devices
1997 Aug 08
15
LOGIC PROGRAMMING
The PLC18V8Z series is fully supported by industry standard
(JEDEC compatible) PLD CAD tools, including Philips
Semiconductors’ SNAP design software package. ABEL
and
CUPL
design software packages also support the PLC18V8Z
architecture.
All packages allow Boolean and state equation entry formats. SNAP,
ABEL and CUPL also accept, as input, schematic capture format.
PLC18V8Z logic designs can also be generated using the program
table entry format, which is detailed on the following pages. This
program table entry format is supported by SNAP only.
With Logic programming, the AND/OR/EX-OR gate input
connections necessary to implement the desired logic function are
coded directly from logic equations using the Program Table.
Similarly, various OMC configurations are implemented by
programming the Architecture Control bits AC1 and AC2. Note that
the configuration cell is automatically programmed based on the
OMC configuration.
In this table, the logic state of variables I, P and B associated with
each Sum Term S is assigned a symbol which results in the proper
fusing pattern of corresponding link pairs, defined as follows:
OUTPUT POLARITY – (O, B)
O, B
S
X
ACTIVE LEVEL
INVERTING
1
CODE
L
O, B
S
X
ACTIVE LEVEL
CODE
H
NON-INVERTING
SP00023
“AND” ARRAY – (I, B)
CODE
–
STATE
DON’T CARE
CODE
O
STATE
INACTIVE
1
CODE
H
STATE
CODE
L
STATE
I, B
I, B
P
P
P
P
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
SP00024
NOTE:
1. A factory shipped unprogrammed device is configured such that all cells are in a conductive state.
ABEL is a trademark of Data I/O Corp.
CUPL is a trademark of Logical Devices, Inc.
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