參數(shù)資料
型號: PLL2124X
英文描述: 6 Channel, 14-Bit, 600ksps Simultaneous Sampling ADC with Shutdown; Package: QFN; No of Pins: 32; Temperature Range: -40°C to +85°C
中文描述: PLL2124X高達50MHz?300MHz的FSPLL |數(shù)據(jù)資料
文件頁數(shù): 5/10頁
文件大?。?/td> 150K
代理商: PLL2124X
SEC ASIC
50MHz~300MHz FSPLL
ANALOG
PLL2108X
FUNCTIONAL DESCRIPTION
A PLL is the circuit synchronizing an output signal (generated by an VCO) with a reference or input signal in
frequency as well as in phase.
The pll2108x can provide frequency multiplication capabilities, but can't
guarantee phase synchronization between FIN and FOUT.
pll2108X consists of the following basic blocks.
-
The phase frequency detector (PFD) detects the phase difference between the reference clock and feedback
clock, then generates UP/DOWN error signals. If reference clock leads feedback clock, UP is high and
DOWN is low. If reference clock lags feedback clock, UP is low and DOWN is high.
-
The charge pump charges or discharges the following loop filter according to UP/DOWN signal.
-
The loop filter suppresses high frequency components in the charge pump voltage (Vctrl), allowing the dc
value to control the VCO frequency.
-
The voltage-controlled oscillator generates the clock signal proportional to control voltage.
Required frequency is produced by appropriate selection of P, M and S dividers.
Fout = Fin*m/(p*s)
m=M+8 , p=P+2 , s=1,2,4,8
- Don't set the value P or M to all zero, that is 000000/ 00000000.
- The range of P and M :
1 <= P <= 62,
- The M and P must be selected considering stability and VCO range.
VCO output frequency range of pll2108x is from 100MHz to 200MHz.
1 <= M <= 248
Digital data format:
Main Divider
Pre Divider
Post Scaler
M7,M6,M5,M4,M3,M2,M1,M0
P5,P4,P3,P2,P1,P0
S1,S0
NOTES
. M[7] -
. P[5]
. S[1]
M[0]: : main-divider
P[0]
: pre-divider
S[0]
: post-scaler
1<=M<=248
1<=P<=62
0<=S<=3
-
-
IMPORTANT NOTICE
-
Please consult with SEC application engineer about the proper selection of M, P, S values.
5/10
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