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參數(shù)資料
| 型號(hào)： | PLL2124X |
| 英文描述： | 6 Channel, 14-Bit, 600ksps Simultaneous Sampling ADC with Shutdown; Package: QFN; No of Pins: 32; Temperature Range: -40°C to +85°C |
| 中文描述： | PLL2124X高達(dá)50MHz?300MHz的FSPLL |數(shù)據(jù)資料 |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大?。?/td> | 150K |
| 代理商： | PLL2124X |
SEC ASIC
50MHz~300MHz FSPLL
ANALOG
PLL2108X
Pin Name
Pin
Usage
Pin Layout Guide
AVDD12D
External
-. Use dedicated power/ground pins for PLL
-. Power cuts are required to provide on-chip isolation
=> between dedicated PLL power/ground and all
other power/ground
-. Use good power and ground source on board
AVSS12D
External
AVDD12A
External
AVSS12A
External
VABB
External
FIN
External
-. Do not place noisy, high frequency and high
power consuming circuitry pads near the FIN.
-. Use proper low jitter reference clock
FOUT
External/Internal
-. Do not place noisy, high frequency and high
power consuming circuitry pads near the FOUT.
-. Internal routing path should be short.
This will minimize loading effect.
-. FOUT signals should not be crossed by any
signals and should not run next to digital signals.
This will minimize capacitive coupling between
the two signals.
FILTER
External
-. Do not place the noisy, high frequency and high
power consuming circuitry pads near the FILTER.
-. Ground shielding is needed for internal routing
path.
-. FILTER routing path should not be crossed by
any signals and should not run next to digital
signals.
-. External loop filter pin should be placed between
analog power and ground to avoid stray coupling
outside the chip and magnetic coupling via bond
wires.
- Loop filter components should be placed as close
as possible.
PWRDN
M[7]~M[0]
P[5]~P[0]
Interanl/External
Internal/External
Internal/External
S[1]~S[0]
Internal/External
9/10
PIN LAYOUT GUIDE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PLL2126X | PLL2126X 20MHz ~ 100MHz FSPLL|Data Sheet |
| PLL2127X | PLL2127X 20MHz ~ 100MHz FSPLL|Data Sheet |
| PLL2128X | PLL2128X 20MHz ~ 100MHz FSPLL|Data Sheet |
| PLLCORE120 | Phase-Locked Loop |
| PLLCORE170 | 12-Bit Rail-to-Rail Micropower DACs in SO-8; Package: PDIP; No of Pins: 8; Temperature Range: -40°C to +85°C |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLL2126X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PLL2126X 20MHz ~ 100MHz FSPLL|Data Sheet |
| PLL2127X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PLL2127X 20MHz ~ 100MHz FSPLL|Data Sheet |
| PLL2128X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PLL2128X 20MHz ~ 100MHz FSPLL|Data Sheet |
| PLL-21-Y3-1 | 制造商:Panduit Corp 功能描述: |
| PLL-22-PO-1 | 功能描述:電線鑒定 Laser, Comp Label, Polyolefin, 7.875" W RoHS:否 制造商:TE Connectivity / Q-Cees 產(chǎn)品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長(zhǎng)度:1 in |
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