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參數(shù)資料
| 型號(hào)： | PLS159A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Programmable Logic(可編程邏輯器件) |
| 中文描述： | 可編程邏輯（可編程邏輯器件） |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大小： | 198K |
| 代理商： | PLS159A |
Philips Semiconductors Programmable Logic Devices
Application Note
AN15
PLS159A primer
Issued June 1988; Revised October 1990
INTRODUCTION
The PLS159A is a programmable logic
sequencer which consists of four dedicated
inputs, four bidirectional I/O’s, eight flip-flops,
thirty two 16-input AND gates, twenty
32-input OR gates, and a complement array.
Each flip-flop has a bidirectional I/O and may
be individually programmed as J-K or D
flip-flop, or switch between the two types
dynamically. The flip-flops will accept data
from the internal logic array or from the
bidirectional I/O, or they may be set or reset
asynchronously from the AND array. The
output polarity of the four bidirectional I/O’s
are programmable and the direction is
controlled by the AND array. Figure 1 is the
logic diagram of PLS159A.
1
October 1990
PROGRAMMING THE PLS159A
The programming table is shown in Table 1
where there is a place for everything that is
shown in Figure 1. The program table is
basically divided into two main sections. The
left hand side of the table, section A,
represents the input side of the AND gates,
while the right hand side, section B,
represents the OR gates sections which
includes the flip-flops and the combinatorial
outputs B(0) to B(3). The flip-flops modes are
defined in section C and the output polarities
of the combinatorial outputs are defined in
section E. The programming symbols are
detailed in Figure 2.
As shown in Table 1, the programming table
is very similar to a truth table. Each column in
section A represents an input to the 32 AND
gates, and each row represents an AND gate
connecting to 17 inputs. Columns I
0
to I
3
represent the 4 dedicated inputs, I
0
to I
3
.
Columns B(I)
0
to B(I)
3
represent the inputs of
the 4 bidirectional I/O, B
0
to B
3
. Columns
Q(P)
0
to Q(P)
7
represent the feedback, F
0
to
F
7
, from the flip-flops (the present state).
Column “C” represents the complement
array.
As shown in Figure 1, the outputs of the AND
gates are connected to an array of OR gates
which, in turn, are connected to either
flip-flops or output circuits. Columns Q(N)
0
to
Q(N)
7
represent the next state which the
flip-flops will be in. Columns B(O)
0
to B(O)
3
represent the combinatorial outputs B
0
to B
3
.
Each row represents an AND gate with 17
inputs each of which may be true and/or
complement and is, therefore, a perfect
decoder. Referring to the programming
symbols in Figure 2, to implement the
equation
Z = A * B * C * D,
all one has to do is to enter one line as
shown in Table 2, term-0.
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| PLS167AA | Fuse-Programmable PLD |
| PLS167AN | 16-Bit Byte Wide, Low Glitch Multiplying DAC with 4-Quadrant Resistors; Package: SSOP; No of Pins: 24; Temperature Range: -40°C to +85°C |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLS159AA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Programmable logic sequencer 16 】 45 】 12 |
| PLS159AF | 制造商:NXP Semiconductors 功能描述: |
| PLS159AN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Programmable logic sequencer 16 】 45 】 12 |
| PLS159AN-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| PLS167/BLA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
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