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參數(shù)資料
| 型號(hào)： | PLS159A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Programmable Logic(可編程邏輯器件) |
| 中文描述： | 可編程邏輯（可編程邏輯器件） |
| 文件頁數(shù)： | 5/11頁 |
| 文件大小： | 198K |
| 代理商： | PLS159A |
Philips Semiconductors Programmable Logic Devices
Application Note
AN15
PLS159A primer
October 1990
5
Figure 2
(cont.)
Q
J
K
T
n
M = DISABLED
ACTION
HOLD
CODE
Q
J
K
T
n
M = DISABLED
ACTION
RESET
CODE
L
Q
J
K
T
n
M = DISABLED
ACTION
SET
CODE
Q
J
K
T
n
ACTION
TOGGLE
CODE
O
–
H
M = DISABLED
“OR” ARRAY – (Q
n
= J-K Type)
T
n
STATUS
INACTIVE
CODE
T
n
STATUS
ACTIVE
CODE
A
T
n
P, R, S
(OR B)
T
n
POLARITY
LOW
CODE
L
POLARITY
HIGH
CODE
H
S
B
S
B
P, R, S
(OR B)
“OR” ARRAY – (S or B), (P), (R)
“EX-OR” ARRAY – (B)
ACTION
DISABLE
CODE
ACTION
ENABLE
4
CODE
ACTION
CONTROL
CODE
ACTION
IDLE
4
CODE
O
–
A
E
n
OE
E
n
OE
E
n
OE
E
n
OE
“OE” ARRAY – (E)
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates.
2. Any gate (T, F
C
, L, P, R, D)
n
will be unconditionally inhibited if any one of the I, B, or Q link pairs is left intact.
3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates T
n
, F
C
.
4. E
= O and E
=
are logically equivalent states, since both cause F
outputs to be unconditionally enabled.
5. These states are not allowed for control gates (L, P, R, D)
n
due to their lack of “OR” array links.
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