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參數(shù)資料
| 型號： | PLS159A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Programmable Logic(可編程邏輯器件) |
| 中文描述： | 可編程邏輯（可編程邏輯器件） |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 198K |
| 代理商： | PLS159A |
Philips Semiconductors Programmable Logic Devices
Application Note
AN15
PLS159A primer
October 1990
7
Notice that only I
0
to I
3
on the left hand side
and B(O)
4
on the right hand side have entries
to implement the equation. All unused
columns are dashed out or dotted out.
To implement the equation
Y=/A * B * /C,
enter one line as shown in Table 2, term-2
where the entry “H” represents the
non-inverting input buffer while the entry “L”
represents the inverting buffer. To have the
AND gate to be unconditionally “High”, dash
out all the inputs of that particular AND gate
as shown in Table 2, term-4. The virgin
condition of the device, as shipped from the
factory, has all connections intact, which
means that the inverting and the
non-inverting buffers of the same inputs are
connected together. Such connection will
cause the AND gate to be unconditionally
“Low” as shown in Table 2, terms 6 and 7.
The unconditional High and Low states are
normally useful only internally and seldom
brought out to the output pins.
To implement the equation
W=A * /B+C * /D,
enter one line for A * /B and another line for
C * /D as shown in Table 2, terms 9 and 10.
Use one line to AND something together; use
different lines to OR something together —
one line per item to be OR’ed.
All the pins which are labelled B’s are
bidirectional I/O pins. Their input buffers are
represented by the B(I) columns on the left
hand side of the programming table. An “H”
entry represents the non-inverting buffer and
an “L” entry represents the inverting buffer.
Their output buffers are represented by the
B(O) columns on the right hand side of the
table. An “A” entry means that the output is
active (connected to the AND gates); a “.”
entry means that the output is inactive (not
connected). The outputs may be
programmed to be inverting or noninverting.
The polarity of each output is determined by
its exclusive OR gate (Figure 1 and Figure 2).
To have a non-inverting output, enter an “H”
in the section labelled “POLARITY” (Table 1,
Section E). To have an inverting output, enter
an “L”. For example, Table 3, terms -0 and -2
implement the equation
Z=/(A * B) and Y=A * B
respectively. The above two equations may
also be implement by term-4 which uses the
same AND gate to drive two OR gates.
Besides being able to have programmable
Active-High or Active-Low output, the
programmable output polarity feature also
low output, the programmable output polarity
feature also allows the user to minimize his
AND term utilization by converting his logic
equation into other forms such as conversion
by De Morgan Theorem.
For example, the equation
X=A+B+C+D
takes four AND terms to implement as shown
in Table 3, terms 6 to 9. By using De Morgan
Theorem, the same equation is changed to
/W=/A * /B * /C * /D
The result is as shown in term 11 — a saving
of three AND terms. The output buffers are
disabled in their virgin states so that they all
behave as inputs. The buffers are enabled or
disabled by their corresponding Control AND
terms D
0
to D
3
(see Figure 1). The Control
AND terms are represented in the
programming table on the last four rows on
the left hand side. Dashing out all the inputs
will cause the output buffer to be
unconditionally enabled, whereas a “0” (zero)
will cause the buffer to be unconditionally
disabled. The buffers may also be controlled
by a logical condition, e.g. A * /B * /C, etc.
There are eight flip-flops on the chip each of
which may be programmed as a J/K or a D
flip-flop, or they may be programmed to
switch dynamically. As shown in Figure 1,
each flip-flop is a J/K to begin with. A 3-State
inverter is connected in between the J and K
inputs of each flip-flop, which when enabled
by the AND gate F
C
, will cause the flip-flop to
function as a D flip-flop. The inverters are
enabled by F
C
through fuses M
0
to M
7
. A “.”
in the F/F Mode entry of the programming
table means that particular fuse is to be
disconnected and that particular flip-flop is to
be J/K. An “A” entry will leave the M fuses
intact, which allow the flip-flop to be D or J/K
as controlled by the output of F
C
(see
Figure 2, “OR” ARRAY — (MODE)). The
inputs to the flip-flops are represented by the
programming table as the next state,
Q(N)
0 to 7
since their inputs are from the OR
array. The outputs of these registers are
connected to their respective 3-State
inverting output buffers, four of which are
controlled by EA and the other four by EB. A
“.” in EA will enable outputs F
0
to F
3
,
whereas a “–” will disable them. An “A” will
allow the output buffers to be controlled by
/OE, pin 11. Table 4, terms 0, 1 and 3
represent the following equations
Q
0
: J=A * C+/B * /E
eq. 1
Q
0
: K=A * /C
eq. 2
Notice that the J input in equation 1 is
represented by the “H” entry in terms-0 and
1, column Q(N)
0
while the K input in equation
2 is represented by the “L” entry in term-3,
column Q(N)
0
. An undefined input, J or K, is
considered “Low”.
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PDF描述 |
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| PLS167AA | Fuse-Programmable PLD |
| PLS167AN | 16-Bit Byte Wide, Low Glitch Multiplying DAC with 4-Quadrant Resistors; Package: SSOP; No of Pins: 24; Temperature Range: -40°C to +85°C |
| PLS167AN-B | 16-Bit Byte Wide, Low Glitch Multiplying DAC with 4-Quadrant Resistors; Package: PDIP; No of Pins: 24; Temperature Range: 0°C to +70°C |
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相關(guān)代理商/技術(shù)參數(shù) |
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| PLS159AA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Programmable logic sequencer 16 】 45 】 12 |
| PLS159AF | 制造商:NXP Semiconductors 功能描述: |
| PLS159AN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Programmable logic sequencer 16 】 45 】 12 |
| PLS159AN-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| PLS167/BLA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
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