- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370007 > PLSI1016E80LT44I (Lattice Semiconductor Corporation) High-Density Programmable Logic PDF資料下載
參數(shù)資料
| 型號(hào)： | PLSI1016E80LT44I |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Density Programmable Logic |
| 中文描述： | 高密度可編程邏輯 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 208K |
| 代理商： | PLSI1016E80LT44I |
5
1996 ISP Encyclopedia
Specifications
ispLSI and pLSI 1016E
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
UNITS
-125
MIN.
–
–
125
TEST
COND.
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions Section.
Table 2-0030-16/125,100, 80
1
4
3
1
( )
-100
MIN.
–
–
100
MAX.
7.5
10.0
MAX.
10.0
13.0
DESCRIPTION
#
2
PARAMETER
A
A
A
1
2
3
Data Prop. Delay, 4PT Bypass, ORP Bypass
Data Prop. Delay, Worst Case Path
Clk. Frequency with Int. Feedback
ns
ns
MHz
–
–
–
–
–
A
–
4
5
6
7
8
Clk. Frequency with Ext. Feedback
Clk. Frequency, Max. Toggle
GLB Reg. Setup Time before Clk., 4 PT Bypass
GLB Reg. Clk. to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clk., 4 PT Bypass
–
–
–
–
–
–
MHz
MHz
ns
ns
ns
–
–
0.0
–
–
–
–
A
–
B
C
B
C
9
GLB Reg. Setup Time before Clk.
10 GLB Reg. Clk. to Output Delay
11 GLB Reg. Hold Time after Clk.
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
5.5
–
0.0
–
5.0
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
–
t
wh
t
wl
t
su3
t
h3
–
–
18 Ext. Sync. Clk. Pulse Duration, High
19 Ext. Sync. Clk. Pulse Duration, Low
3.0
3.0
4.0
4.0
ns
ns
–
–
20 I/O Reg. Setup Time before Ext. Sync. Clk. (Y2, Y3) 3.0
21 I/O Reg. Hold Time after Ext. Sync. Clk. (Y2, Y3)
–
–
–
–
ns
ns
0.0
100
167
5.0
4.5
–
–
5.5
–
10.0
–
12.0
12.0
7.0
7.0
–
–
77
125
7.0
0.0
8.0
0.0
6.5
3.5
0.0
5.0
6.0
13.5
15.0
15.0
9.0
9.0
–
–
( )
1
-80
MIN. MAX.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
15.0
18.5
84.0
57.0
100
8.5
8.0
0.0
9.5
9.5
0.0
17.0
10.0
20.0
20.0
10.5
10.5
5.0
5.0
0.0
4.5
–
–
–
–
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PLSI1032-60LJ | High-Density Programmable Logic |
| PLSI1032-60LJI | KPSE06F14-15PF0 |
| PLSI1032-60LT | High-Density Programmable Logic |
| PLSI1032-80LJ | High-Density Programmable Logic |
| PLSI1032-80LT | High-Density Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLSI1024-50LJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| PLSI1024-60LH/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| PLSI1024-60LJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| PLSI1024-60LJI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| PLSI1024-80LJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。