參數(shù)資料
型號: PLSI1016E80LT44I
廠商: Lattice Semiconductor Corporation
英文描述: High-Density Programmable Logic
中文描述: 高密度可編程邏輯
文件頁數(shù): 9/15頁
文件大小: 208K
代理商: PLSI1016E80LT44I
9
1996 ISP Encyclopedia
Specifications
ispLSI and pLSI 1016E
Power Consumption
Power Consumption in the ispLSI and pLSI 1016E device
depends on two primary factors: the speed at which the
device is operating and the number of Product Terms
used. Figure 3 shows the relationship between power
and operating speed.
80
110
0
20
40
60
f
max (MHz)
80
100 120 140
I
C
Notes: Configuration of four 16-bit counters
Typical current at 5V, 25
°
C
ispLSI and pLSI 1016E
100
0127B-16-80-isp/1016
ICC can be estimated for the ispLSI and pLSI 1016E using the following equation:
ICC(mA) = 23 + (# of PTs * 0.52) + (# of nets * max freq * 0.004)
Where:
# of PTs = Number of product terms used in design
# of nets = Number of signals used in device
Max freq = Highest clock frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB loads
on average exists and the device is filled with four 16-bit counters. These values are for estimates only. Since the
value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
120
130
90
Figure 3. Typical Device Power Consumption vs fmax
Maximum GRP Delay vs GLB Loads
GLB Load
1
3
1
4
8
16
G
2
16E GRP/GLB.eps
ispLSI and pLSI 1016E-125
ispLSI and pLSI 1016E-100
12
ispLSI and pLSI 1016E-80
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