參數(shù)資料
型號(hào)： PLSI1032-80LJ
廠商： LATTICE SEMICONDUCTOR CORP
元件分類(lèi)： PLD
英文描述： High-Density Programmable Logic
中文描述： EE PLD, 20 ns, PQCC84
封裝： PLASTIC, LCC-84
文件頁(yè)數(shù)： 12/19頁(yè)
文件大?。?/td> 256K
代理商： PLSI1032-80LJ
Specifications
ispLSI and pLSI 1032
12
1996 ISP Encyclopedia
Pin Description
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
Input/Output – This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
Input – This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
* For ispLSI 1032 Only
Name
PLCC Pin Numbers
Description
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
26,
30,
34,
38,
45,
49,
53,
57,
68,
72,
76,
80,
3,
7,
11,
15,
27,
31,
35,
39,
46,
50,
54,
58,
69,
73,
77,
81,
4,
8,
12,
16,
28,
32,
36,
40,
47,
51,
55,
59,
70,
74,
78,
82,
5,
9,
13,
17,
29,
33,
37,
41,
48,
52,
56,
60,
71,
75,
79,
83,
6,
10,
14,
18
IN 4 - IN 7
67,
84,
2,
19
Dedicated input pins to the device.
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
ispEN*/NC
23
SDI*/IN 0
25
MODE*/IN 1
42
SDO*/IN 2
44
SCLK*/IN 3
61
GND
V
CC
1,
21,
22,
65
43,
64
Ground (GND)
V
CC
RESET
24
Y0
20
Y1
66
Y2
63
Y3
62
Table 2-0002A-32-isp
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