參數(shù)資料
型號(hào)： PLSI1032-80LJ
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： High-Density Programmable Logic
中文描述： EE PLD, 20 ns, PQCC84
封裝： PLASTIC, LCC-84
文件頁(yè)數(shù)： 8/19頁(yè)
文件大?。?/td> 256K
代理商： PLSI1032-80LJ
Specifications
ispLSI and pLSI 1032
8
1996 ISP Encyclopedia
ispLSI and pLSI 1032 Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
4 PT Bypass
#33
20 PT
XOR Delays
Control
PTs
#444
LGRP
Delay
#27, 29,
30, 31, 32
Input
Register
RST
DiClock
I/O Pin
(Input)
Y0
Y1,2,3
D
Q
GRP 4
#28
GLB Reg Bypass
#37
ORP Bypass
#46
D
Q
RST
RE
OE
CK
I/O Reg Bypass
#20
I/O Cell
ORP
GLB
GRP
I/O Cell
#21 - 25
#34, 35, 36
#53, 54
#50
#45
Reset
Ded. In
#26
#55
#55
#38, 39,
40, 41
#48, 49
#47
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
1
t
su
= Logic + Reg su - Clock (min)
=
(
t
iobp +
t
grp4 +
t
20ptxor
)
+
(
t
gsu
) - (
t
iobp +
t
grp4 +
t
ptck(min)
)
=
(
#20 + #28 + #35
)
+
(
#38
) - (
#20 + #28 + #44
)
5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (2.0 + 2.0 + 3.5)
t
h
= Clock (max) + Reg h - Logic
=
(
t
iobp +
t
grp4 +
t
ptck(max)
)
+
(
t
gh
) - (
t
iobp +
t
grp4 +
t
20ptxor
)
=
(
#20 + #28 + #44
)
+
(
#39
) - (
#20 + #28 + #35
)
4.0 ns = (2.0 + 2.0 + 7.5) + (4.5) - (2.0 + 2.0 + 8.0)
t
co
= Clock (max) + Reg co + Output
=
(
t
iobp +
t
grp4 +
t
ptck(max)
)
+
(
t
gco
)
+
(
t
orp +
t
ob
)
=
(
#20 + #28 + #44
)
+
(
#40
)
+
(
#45 + #47
)
19.0 ns = (2.0+ 2.0 +7.5) + (2.0) + (2.5 + 3.0)
Derivations of
t
su,
t
h and
t
co from the Clock GLB
1
t
su
= Logic + Reg su - Clock (min)
=
(
t
iobp +
t
grp4 +
t
20ptxor
)
+
(
t
gsu
) - (
t
gy0(min) +
t
gco +
t
gcp(min)
)
=
(
#20 + #28 + #35
)
+
(
#38
) - (
#50 + #40 + #52
)
5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (4.5 + 2.0 + 1.0)
t
h
= Clock (max) + Reg h - Logic
=
(
t
gy0(max) +
t
gco +
t
gcp(max)
)
+
(
t
gh
) - (
t
iobp +
t
grp4 +
t
20ptxor
)
=
(
#50 + #40 + #52
)
+
(
#39
) - (
#20 + #28 + #35
)
4.0 ns = (4.5 + 2.0 + 5.0) + (4.5) - (2.0 + 2.0 + 8.0)
t
co
= Clock (max) + Reg co + Output
=
(
t
gy0(max) +
t
gco +
t
gcp(max)
)
+
(
t
gco
)
+
(
t
orp +
t
ob
)
=
(
#50 + #40 + #52
)
+
(
#40
)
+
(
#45 + #47
)
19.0 ns = (4.5 + 2.0 + 5.0) + (2.0) + (2.5 + 3.0)
1. Calculations are based upon timing specifications for the ispLSI and pLSI 1032-80.
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