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PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7341 S/UNI-IMA-84
DATASHEET
PMC-2000223
ISSUE 4
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
xiii
FIGURE 38- ANY-PHY TRANSMIT SLAVE.................................................... 390
FIGURE 39- UTOPIA L2 MULTI-PHY RECEIVE SLAVE................................ 391
FIGURE 40- UTOPIA L2 SINGLE-PHY RECEIVE SLAVE ............................. 391
FIGURE 41- ANY-PHY RECEIVE SLAVE ...................................................... 392
FIGURE 42- SDRAM READ TIMING ............................................................. 393
FIGURE 43- SDRAM WRITE TIMING............................................................ 394
FIGURE 44- SDRAM REFRESH.................................................................... 395
FIGURE 45- POWER UP AND INITIALIZATION SEQUENCE....................... 396
FIGURE 46- MICROPROCESSOR INTERFACE READ TIMING................... 402
FIGURE 47- MICROPROCESSOR INTERFACE WRITE TIMING................. 404
FIGURE 48- RSTB TIMING............................................................................ 405
FIGURE 49- SYNCHRONOUS I/O TIMING ................................................... 405
FIGURE 50- SBI FRAME PULSE TIMING ..................................................... 409
FIGURE 51- SBI DROP BUS TIMING............................................................ 410
FIGURE 52- SBI ADD BUS TIMING................................................................411
FIGURE 53- SBI ADD BUS COLLISION AVOIDANCE TIMING ......................411
FIGURE 54- JTAG PORT INTERFACE TIMING............................................. 413
FIGURE 55- 416 PIN PBGA –27X27 MM BODY – (P SUFFIX) ..................... 415