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參數(shù)資料
| 型號： | PowerPC 405CR |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC Embedded Controllers(32位RISC結(jié)構(gòu)嵌入式控制器) |
| 中文描述： | 32位RISC嵌入式控制器（32位的RISC結(jié)構(gòu)嵌入式控制器） |
| 文件頁數(shù)： | 24/42頁 |
| 文件大?。?/td> | 565K |
| 代理商： | POWERPC 405CR |
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PowerPC 405CR Embedded Controller Data Sheet
24
Signal Functional Description
(Part 1 of 6)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
SDRAM Interface
MemData0:31
Memory Data bus
Notes:
1. MemData0 is the most significant bit (msb)
2. MemData31 is the least significant bit (lsb)
I/O
3.3V LVTTL
4
MemAddr12:0
Memory Address bus
O
3.3V LVTTL
BA0:1
Bank Address supporting up to four internal banks
O
3.3V LVTTL
RAS
Row Address Strobe
O
3.3V LVTTL
CAS
Column Address Strobe
O
3.3V LVTTL
DQM0:3
DQM for byte lanes 0 (MemData0:7),
1 (MemData8:15),
2 (MemData16:23), and
3 (MemData24:31)
O
3.3V LVTTL
DQMCB
DQM for ECC check bits
O
3.3V LVTTL
ECC0:7
ECC check bits 0:7
I/O
3.3V LVTTL
4
BankSel0:3
Select up to four external SDRAM banks
O
3.3V LVTTL
WE
Write Enable
O
3.3V LVTTL
ClkEn0:1
SDRAM Clock Enable
O
3.3V LVTTL
MemClkOut0:1
Two copies of an SDRAM clock allows, in some cases, glueless
SDRAM attach without requiring this signal to be repowered by a
PLL or zero-delay buffer.
O
3.3V LVTTL
External SLAVE Peripheral Interface
PerData0:31
Peripheral data bus used by PPC405CR when not in external
master mode, otherwise used by external master
Note:
PerData0 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
PerAddr0:31
Peripheral address bus used by PPC405CR when not in external
master mode, otherwise used by external master.
Note:
PerAddr0 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
PerPar0:3
Peripheral byte parity signals
I/O
5V tolerant
3.3V LVTTL
1
PerWBE0:3
PerWE
As outputs, these pins can act as byte-enables which are valid for
an entire cycle or as write-byte-enables which are valid for each
byte on each data transfer, allowing partial word transactions. As
outputs, pins are used by either peripheral controller or DMA
controller depending upon the type of transfer involved. Used as
inputs when external bus master owns the external interface
I/O
5V tolerant
3.3V LVTTL
1, 2
PerCS0
Peripheral chip select bank 0
O
5V tolerant
3.3V LVTTL
2
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