參數(shù)資料
型號: PowerPC 440
廠商: IBM Microeletronics
英文描述: 32-bit RISC PowerPC Embedded Processor Cores(32位 RISC PowerPC 嵌入式處理器)
中文描述: 32位RISC PowerPC嵌入式處理器內(nèi)核(RISC的32位的PowerPC嵌入式處理器)
文件頁數(shù): 2/18頁
文件大?。?/td> 317K
代理商: POWERPC 440
PowerPC 440 Core
09/21/1999
Page 2 of 18
Overview
The PowerPC 440 CPU core is the latest addition to IBM’s family of 32-bit RISC PowerPC embedded
processor cores. The PPC440’s high-speed, superscalar design and Book E Enhanced PowerPC
Architecture
put it at the leading edge for high performance system-on-a-chip (SOC) designs. The
PPC440 core marries the performance and features of standalone microprocessors with the flexibility,
low power, and modularity of embedded CPU cores.
Target Applications
The PPC440 Core is primarily designed for applications in which maximum performance and extensive
peripheral integration are the critical selection criteria.
Target market segments for the PPC440 core include:
Consumer applications including digital cameras, video games, set-top boxes, and internet appliances
Office automation products such as laser printers, thin-client systems, and sub-notebooks
Storage and networking products such as RAID controllers, routers, ATM switches, cellular
basestations, and network cards
Features
2-way superscalar design
Out-of-order issue, execution, and completion
Dynamic branch prediction
Single-cycle branch latency
Three execution pipelines
Single-cycle throughput on 32x32 multiply
24 DSP operations (16x16+32->32, MAC with single-cycle throughput)
Real-time non-invasive instruction trace
Typical Application
A typical system on a chip design with the PPC440 Core uses the CoreConnect
TM
bus structure for system
level communication. High bandwidth peripherals and the PPC440 core communicate with one another
over the processor local bus (PLB). Less demanding peripherals share the on-chip peripheral bus (OPB)
and communicate to the PLB through the OPB Bridge. The PLB and OPB provide common interfaces for
peripherals and enable quick turnaround, custom solutions for high volume applications.
Figure 1 shows an example PPC440 Core-based system on a chip, illustrating the two-level bus structure
and modular core-based design.
相關(guān)PDF資料
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PowerPC 602 32-bit implementation Reduced Instruction Set Computer (RISC) Microprocessors.(32位精簡指令集微處理器)
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