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參數(shù)資料
| 型號(hào)： | PowerPC 440 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC PowerPC Embedded Processor Cores(32位 RISC PowerPC 嵌入式處理器) |
| 中文描述： | 32位RISC PowerPC嵌入式處理器內(nèi)核（RISC的32位的PowerPC嵌入式處理器） |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 317K |
| 代理商： | POWERPC 440 |
PowerPC 440 Core
09/21/1999
Page 5 of 18
Figure 3 - PPC440 CPU Pipeline
Instruction Fetch and Pre-decode
During the Instruction Fetch stage (IFTH), an entire cache line (eight words) is read into the instruction
cache line read buffer. From there, the next two instructions in the pre-decode buffers PDCD0 and
PDCD1 during the PDCD stage. The instruction cache is virtually indexed and tagged, and translation is
performed in parallel with the cache access.
Branch Unit
The PPC440 uses a Branch History Table (BHT) to maintain dynamic branch prediction of conditional
branches. To perform dynamic branch prediction, a 2-bit counter in the BHT is used to decide whether
prediction should agree or disagree with the normal PowerPC static branch prediction. The counter
counts up if branch determination agrees, and down if it disagrees. Once the counter saturates, it can only
count away from saturation. Therefore, four valid states exist: “Strongly agree”, “Agree”, “Disagree”,
and “Strongly disagree”. By agreeing or disagreeing with static branch prediction, different branches can
use the same counter in the BHT and have opposite static predictions, without the machine necessarily
mispredicting a branch.
The Branch Target Address Cache (BTAC) is used to predict branches and deliver their target addresses
before the instruction cache can deliver the same data. It is accessed during IFTH, whereas normal
branch prediction would not occur until PDCD, and therefore avoids a one cycle penalty. The BTAC is
made up of an odd and even BTAC containing eight entries each. Only unconditional branches and bdnz
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