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參數(shù)資料
| 型號： | PowerPC 740 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Microprocessor(32位精簡指令集嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位精簡指令集嵌入式微處理器） |
| 文件頁數(shù)： | 16/48頁 |
| 文件大小： | 608K |
| 代理商： | POWERPC 740 |
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Page 16
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
μ
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
60x Bus Output AC Specifications
The following table provides the 60x bus output AC timing specifications for the 750 as defined in Figure 5.
Output timing specification for the L2 bus are provided in the Section “L2 Bus Output AC Specifications,” on
page 21.
60X Bus Output AC Timing Specifications for the 750
1
See Table “Recommended Operating Conditions,” on page 9 for operating conditions, C
L
= 50pF
2
Num
Characteristic
All Frequencies
Unit
Notes
Minimum
Maximum
12
SYSCLK to Output Driven (Output Enable Time)
0.5
ns
8
13
SYSCLK to Output Valid (TS, ABB, ARTRY, DBB, and TBST)
–
4.5
ns
5
14
SYSCLK to all other Output Valid (all except TS, ABB, ARTRY,
DBB, and TBST)
–
5.0
ns
5
15
SYSCLK to Output Invalid (Output Hold)
1.0
ns
3, 8, 9
16
SYSCLK to Output High Impedance (all signals except ABB,
ARTRY, and DBB)
–
6.0
ns
8
17
SYSCLK to ABB and DBB high impedance after precharge
–
1.0
t
SYSCLK
4, 6, 8
18
SYSCLK to ARTRY high impedance before precharge
–
5.5
ns
8
19
SYSCLK to ARTRY precharge enable
0.2
×
t
SYSCLK
+ 1.0
ns
3, 4, 7
20
Maximum delay to ARTRY precharge
1
t
SYSCLK
4, 7
21
SYSCLK to ARTRY high impedance after precharge
2
t
SYSCLK
4, 7, 8
Note:
1. All output specifications are measured from Vm of the rising edge of SYSCLK to Vm of the signal in question. Both input and output timings are mea-
sured at the pin.
2. All maximum timing specifications assume C
L
= 50pF.
3. This minimum parameter assumes CL = 0pF.
4. t
is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration of the parameter in question.
5. This footnote has been deleted.
6. Nominal precharge width for ABB and DBB is 0.5 t
SYSCLK
.
7. Nominal precharge width for ARTRY is 1.0 t
SYSCLK
.
8. Guaranteed by design and characterization, and not tested.
9. Connecting L2_TSTCLK to GND no longer provides additional Output Hold. For new designs, L2_TSTCLK should be pulled up to OVdd, but it can be
left connected to GND in Legacy systems.
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