參數(shù)資料
型號: PowerPC 740
廠商: IBM Microeletronics
英文描述: 32-Bit Embedded Microprocessor(32位精簡指令集嵌入式微處理器)
中文描述: 32位嵌入式微處理器(32位精簡指令集嵌入式微處理器)
文件頁數(shù): 18/48頁
文件大?。?/td> 608K
代理商: POWERPC 740
Page 18
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
μ
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
L2 Clock AC Specifications
The following table provides the L2CLK output AC timing specifications for the 750 as defined in Figure 6.
L2CLK Output AC Timing Specifications
See Table “Recommended Operating Conditions,” on page 9, for operating conditions.
Num
Characteristic
Min
Max
Unit
Notes
L2CLK frequency
80
250
MHz
1, 5
22
L2CLK cycle time
4.0
12.5
ns
23
L2CLK duty cycle
50
%
2
Internal DLL-relock time
640
L2CLK
4
L2CLK jitter
±1
50
ps
3, 6
L2CLK skew
0
ps
7
Note:
1. L2CLK outputs are L2CLKOUTA, L2CLKOUTB and L2SYNC_OUT pins. The internal design supports higher L2CLK frequencies. Consult IBM Pow-
erPC Application Engineering (ppcsupp@us.ibm.com) before operating the L2 SRAMs above 250 MHz. The L2CLK frequency to core frequency set-
tings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum or minimum operating
frequencies. L2CLKOUTA and L2CLKOUTB must have equal loading.
2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
3. The major component of L2CLK jitter is passed through from SYSCLK. While SYSCLK jitter is less then
±1
50 ps, L2CLK jitter is also less than
±1
50 ps.
SYSCLK jitter in excess of
±1
50 ps causes L2CLK jitter to exceed
±1
50 ps.
4. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to compute the actual time
duration in nanoseconds. Re-lock timing is guaranteed by design and characterization, and is not tested.
5. The L2CR [L2SL] bit should be set for L2CLK frequencies less than 110MHz.
6. Guaranteed by design and characterization, not tested.
7. Skew between the L2 output clocks is included in the other timing specs.
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