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參數(shù)資料
| 型號： | PowerPC 750 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Microprocessor(32位精簡指令集嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位精簡指令集嵌入式微處理器） |
| 文件頁數(shù)： | 14/46頁 |
| 文件大?。?/td> | 610K |
| 代理商： | POWERPC 750 |
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Page 10
Version 2.0
Datasheet
9/30/99
PowerPC 750 SCM RISC Microprocessor
PID8p-750
Preliminary Copy
AC Electrical Characteristics
This section provides the AC electrical characteristics for the PID8p-750. After fabrication, parts are sorted by
maximum processor core frequency as shown in the Section “Clock AC Specifications,” on page 10, and
tested for conformance to the AC specifications for that frequency. These specifications are for 300MHz
through 400MHz processor core frequencies. The processor core frequency is determined by the bus
(SYSCLK) frequency and the settings of the PLL_CFG(0-3) signals. Parts are sold by maximum processor
core frequency; see Section “Ordering Information,” on page 40.
Clock AC Specifications
The following table provides the clock AC timing specifications as defined in Figure 2.
Clock AC Timing Specifications
8
See Table “Recommended Operating Conditions1,2,3,” on page 6, for operating conditions.
Num
Characteristic
300*, 333*, 350*, 366, 375MHz
400, 433, 450, 466, 500MHz
Unit
Notes
Min
Max
Min
Max
Processor fre-
quency
200
As per specified speed
250
As per specified speed
MHz
SYSCLK frequency
25
100
31
100
MHz
1
1
SYSCLK cycle time
10
40
10
32
ns
2,3
SYSCLK rise and
fall time
–
1.0
–
1.0
ns
2,3
4
SYSCLK duty cycle
measured at OV
DD
/
2
40
60
40
60
%
3,7
SYSCLK jitter
–
±
150
–
±
150
ps
4,3
Internal PLL relock
time
–
100
–
100
μ
s
5
Note:
1. Caution: The SYSCLK frequency and the PLL_CFG[0-3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) fre-
quency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0-3] signal
description in Section “PLL Configuration,” on page 30 for valid PLL_CFG[0-3] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.5v to 1.5v
3. Timing is guaranteed by design and characterization, and is not tested.
4. The total input jitter (short term and long term combined) must be under
±
150ps.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time required for PLL lock
after a stable V
and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time
during the power-on reset sequence.
6. * Subject to availability - see your marketing representative.
7. Duty cycle for 1.8, 2.5, and 3.3v I/Os.
8. SYSCLK input levels must not be higher than the absolute maximum ratings table for V
IN
. See Table , “Absolute Maximum Ratings,” on page 6.
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