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參數(shù)資料
| 型號： | PowerPC 750 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Microprocessor(32位精簡指令集嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位精簡指令集嵌入式微處理器） |
| 文件頁數(shù)： | 5/46頁 |
| 文件大小： | 610K |
| 代理商： | POWERPC 750 |
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9/30/99
Version 2.0
Datasheet
Page 1
PowerPC 750 SCM RISC Microprocessor
Preliminary Copy
PID8p-750
Preface
The PowerPC PID8p-750 microprocessor is an implementation of the PowerPC
TM
family of reduced instruc-
tion set computer (RISC) microprocessors. In this document, the term “PID8p-750” is used as an abbreviation
for the phrase “PowerPC 750 SCM RISC Microprocessor Family: PID8p-750 microprocessor.”
This document contains pertinent physical characteristics of the PID8p-750 Single Chip Modules (SCM) and
covers the following topics:
Topic
Overview (page 2)
Features (page 3)
General Parameters (page 5)
Electrical and Thermal Characteristics (page 6)
PowerPC PID8p-750 Microprocessor Pin Assignments (page 23)
PowerPC PID8p-750 Microprocessor Pinout Listings (page 24)
PowerPC PID8p-750 Microprocessor Package Description (page 27)
System Design Information (page 30)
Ordering Information (page 40)
New features/deletions for rev level dd3.x:
Selectable I/O voltages on 60X bus (pin W1) and L2 bus (pin A19). See Table , “Recommended Operating
Conditions1,2,3,” on page 6. Older revs must leave these pins “no connect” or “tied high” for 3.3v I/Os. AC
timings are the same for all I/O voltage modes unless otherwise noted. The 1.8v I/O is selected by tying
the I/O select pin to ground. If a pull down resistor is necessary, the resistor value must be no more than
10 ohms.
60X bus to core frequency now also supports the 10x ratio. See Table , “PID8p-750 Microprocessor PLL
Configuration,” on page 30 for how to set this ratio.
Extra output hold on the 60X bus by L2_TSTCLK pin tied low is no longer available. The L2_TSTCLK pin
must now be tied to OV
DD
for normal operation. See Table , “60X Bus Output AC Timing Specifications
1
,”
on page 13.
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