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參數(shù)資料
| 型號： | PP155 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 21/31頁 |
| 文件大小： | 600K |
| 代理商： | PP155 |
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Altera Corporation
21
PPP Packet Processor 155 Mbps MegaCore Function (PP155) User Guide
Specifications
S
1
DELFCS
1
RW
0: Store FCS with received packet.
1: Delete FCS from received frame.
If cleared, the packet is delivered to the Atlantic interface
with the FCS appended. Setting this bit causes the receiver
to remove the FCS before sending the packet to the Atlantic
interface. Users may set this bit to improve the performance
of the Atlantic interface or to simplify downstream
processing of the packet. This function requires that the
crclen bit be set properly.
0
ENABLE
0
RW
0: Disable packet reception.
1: Enable packet reception.
Clearing this bit to zero places the internal state variables in
the idle condition, clears the status register, and all receive
performance monitor counts (good, FCS, runt, abort).
Setting it enables all functions.
0
RX_IS - Receive Interrupt Register - ’h02
Field
Bits
Access
Function
Default
GOOD
4
RW1C
Set if a good packet is received.
This is set if a legal, correct packet is received.
0
UNALIGNED
3
RW1C
Set if receiver is unaligned.
This is set when the receive aligner is not in the aligned
state. To determine when the aligner has regained
alignment, software should read and clear this bit
periodically until it stays cleared. Clearing align in the
control register prevents this bit from being set, but does not
clear the bit.
0
FCS
2
RW1C
Set if an FCS error occurs.
This is set if a packet with an incorrect FCS is received.
0
ABORT
1
RW1C
Set if a receive packet is aborted.
This is set if a packet terminated with an abort sequence is
received.
0
RUNT
0
RW1C
Set if a runt packet is received.
This is set if an illegally short packet is received.
0
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