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Altera Corporation
Getting Started
PPP Packet Processor 155 Mbps MegaCore Function (PP155) User Guide
1.
Create your custom design instantiating a PP155.
2.
Synthesize the design using your third-party EDA tool. Your EDA
tool should treat the PP155 instantiation as a black box by either
setting attributes or ignoring the instantiation.
3.
After compilation, generate a hierarchical netlist file in your third-
party EDA tool.
4.
Open your netlist file in the Quartus software.
5.
Add the pre-synthesized and encrypted
.e.vqm.v
file from your
working directory.
Using the Quartus Software
1.
Select
Compile mode
(Processing menu).
2.
Specify the Compiler settings in the
Compiler Settings
dialog box
(Processing menu) or use the Compiler Settings wizard.
3.
Specify the user libraries for the project and the order in which the
Compiler searches the libraries.
4.
Specify the input settings for the project. Choose
EDA Tool Settings
(Project menu). Select
Custom EDIF
in the Design entry/ synthesis
tool list. Click
Settings
. In the
EDA Tool Input Settings
dialog box,
make sure that the relevant tool name or option is selected in the
Design Entry/Synthesis Tool
list.
5.
Depending on the type of output file you want, specify Verilog HDL
output settings or VHDL output settings in the
General Settings
dialog box (Project menu). Use the
1993 V HDL language
option.
6.
Add the pre-synthesized and encrypted
.e.vqm.v
file from your
working directory.
7.
Compile your design. The Quartus Compiler synthesizes and
performs place-and-route on your design, and generates output and
programing files.
8.
Import your Quartus-generated output files (
.edo
,
.vho
,
.vo
, or .
sdo
)
into your third-party EDA tool for post-route, device-level, and
system-level simulation.