參數(shù)資料
型號(hào)： PPC405EX-SpAfffTx
廠商： Applied Micro Circuits Corp.
英文描述： PowerPC 405EX Embedded Processor
中文描述： 嵌入式處理器的PowerPC 405EX
文件頁數(shù)： 8/67頁
文件大?。?/td> 457K
代理商： PPC405EX-SPAFFFTX
PPC405EX – PowerPC 405EX Embedded Processor
8
AMCC Proprietary
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
Power PC 405 Processor
The PPC405 processor is a fixed-point, 32-bit RISC unit.
Features include:
Five-stage pipeline with single-cycle execution of most instructions, including loads and stores
Separate, configurable 16 KB D- and I-caches, both two-way set associative
Thirty-two 32-bit general purpose registers (GPRs)
Unaligned load/store support
Hardware multiply/divide
Parity detection and reporting for the instruction cache, data cache, and translation look-aside buffer (TLB)
Double word instruction fetch from cache
Translation of the four GB logical address space into physical addresses
Built-in timer and debug support
Power management
DCR interface is 32 bits wide
Selectable processor vs. bus clock ratios (N:1 ratio only, where N =1, 2, 3,or 4 )
Internal Buses
The PPC405EX contains four internal buses: the processor local bus (PLB), the Advanced High-Performance Bus
(AHB), the on-chip peripheral bus (OPB), and the device control register (DCR) bus. High performance devices
such as the processor, the DDR SDRAM memory controller, PCI Express, the Ethernet MAL, and DMA utilize the
PLB. Lower bandwidth I/O interfaces such as communications and timer interfaces utilize the OPB. The daisy-
chained DCR bus provides a lower bandwidth path for passing status and control information between the
processor and the other on-chip peripheral functions.
PLB
The Processor Local Bus (PLB) is a high-performance on-chip bus used to connect PLB-equipped master and
slave devices to the PPC405 CPU. It provides a 128-bit data path with 64-bit addressing and operates up to
200MHz. There are bridges between the PLB and the OPB.
Features include:
Separate and simultaneous 6.4GB/s read and write data paths
Decoupled address and data buses
Address pipelining
Late master request abort capability
Hidden (overlapped) bus request/grant protocol
Bus arbitration-locking mechanism
Byte-enable capability allows for unaligned half word transfers and 3-B transfers
Support for 32- and 64-B burst transfers
Read word address capability
Sequential burst protocol
Guarded and unguarded memory transfers
Simultaneous control, address, and data phases
DMA buffered, flyby, peripheral-to-memory, memory-to-peripheral, and DMA memory-to-memory operations
AHB
The Advanced High-Performance Bus (AHB) is dedicated to the USB OTG 2.0.
Features include:
32-bit data path
32-bit address
Synchronous to the PLB
From 60MHz to 100MHz.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPC405EX-SPD400T 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 600 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays
PPC405EX-SPD533T 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 600 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays
PPC405EX-SPD600T 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 600 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays
PPC405EX-SSA333T 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 533 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays
PPC405EX-SSA400T 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 533 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays
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