參數(shù)資料
型號(hào)： PRODUCT
英文描述： Product Selection Guide 2002
中文描述： 產(chǎn)品選型指南2002
文件頁數(shù)： 20/26頁
文件大?。?/td> 1061K
代理商： PRODUCT
17
Parallel
GMII
MI
Management
(M)
LED Drivers
10/100BaseT
Transmtter/Receiver
AutoNegotiation
JTAG
Scramber
Descrambler
Controler
Interface
MUX
Tx/Rx
Interface
wth
MDIX
MDC/
MDIO
Test
Pair B
Pair A
Pair C
Pair D
1000BaseTX
Transmtter/Receiver
4B/5B
EnDec
Manchester
EnDec
1000BaseT PMA
-Adaptive Equalizer
-Echo/Next Cancellers
-BLWCorrection
-Slicer/PAM5
1000BaseT PCS
-Side-StreamScramber
-Data Scramber
-Convoutional Encoder
-Symbo Scrambe
Fully integrated single Channel 10/100 and
1000 Mbits Ethernet Physical Layer (PHY)
Meets or exceeds all applicable IEEE
802.3ab Gigabit Ethernet Standard for
1000BaseTX,100BaseTX, and 10BaseT
Ultra Low Power - <1.0W Total
Wake On LAN Support
On Chip Echo and Cross-talk
cancellation
Auto-negotiates between 10/100/1000
Mbits
MAC Interface:
- 10M and 100M - MII
- 1000M - GMII
- User programmable GMII pin ordering
Management Interface (MI) using
MDC/MDIO for Register and Interrupt
Configuration and Status Outputs
Designed for Manufacturability:
- Full scan plus logic BIST
- Memory BIST
- JTAG support
Automatic Crossover (Auto-MDIX) for
Transmit and Receive Twisted Pair
Input/Outputs - 10/100/1000 Mbits
Flexible Management controls
Programmable PHY Address
Minimum External Components
1.8v Digital process, 0.18mm
LED support - Link, Activity, Collision,
Transmit and Receive indicator or user
programmable
Uses standard 1:1 Magnetics
Only two Power supplies: 1.8V (core
and analog) and 2.5V (I/0 and
analog)
- 3.3V available for greater system
flexibility
128-lead PQFP Package
(14mm X 20mm)
L80601
LowPower 10/100/100 Ggabt
Ethernet Physical Layer (PHY)
L80601 Block Diagram
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