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| 型號(hào)： | PSD304R |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯,無(wú)SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，無(wú)的SRAM，19余個(gè)可編程輸入/輸出，通用PLD的有16個(gè)輸入） |
| 文件頁(yè)數(shù)： | 16/127頁(yè) |
| 文件大?。?/td> | 682K |
| 代理商： | PSD304R |
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PSD3XX Famly
2-16
The PSD3XX has three I/O ports (Ports A, B, and C) that are configurable at the bit level.
This permits great flexibility and a high degree of customization for specific applications. The
following is a description of each port. Figure 4 shows the pin structure of Port A.
Port A in Multiplexed Address/Data Mode
The default configuration of Port A is I/O. In this mode, every pin can be set as an input or
output by writing into the respective pin’s direction flip flop (DIR FF, in Figure 4). As an
output, the pin level can be controlled by writing into the respective pin’s data flip flop
(DFF, in Figure 4). When DIR FF = 1, the pin is configured as an output. When DIR FF = 0,
the pin is configured as an input. The controller can read the DIR FF bits by accessing the
READ DIR register; it can read the DFF bits by accessing the READ DATA register.
Port A pin levels can be read by accessing the READ PIN register. Individual pins can be
configured as CMOS or open drain outputs. Open drain pins require external pull-up
resistors. For addressing information, refer to Tables 6 and 7.
Alternatively, each bit of Port A can be configured as a low-order latched address bus bit.
The address is provided by the port address latch, which latches the address on the trailing
edge of ALE. PA0–PA7 can become A0–A7, respectively. This feature enables the user
generate low-order address bits to access external peripherals or memory that require
several low-order address lines.
Another mode of Port A, i.e., Track Mode (CPAF2 = 1) sets the entire port to track the inputs
AD0/A0–AD7/A7, depending on specific address ranges defined by the PAD’s CSADIN,
CSADOUT1, and CSADOUT2 signals. This feature lets the user interface the microcontroller
to shared external resources without requiring external buffers and decoders. In this mode,
the port is effectively a bi-directional buffer. The direction is controlled by using the input
signals ALE, RD/E or RD/E/DS, WR/V
PP
or R/W, and the internal PAD outputs CSADOUT1,
CSADOUT2 and CSADIN (see Figure 5). When CSADOUT1 and ALE are true, the address
on the input AD0/A0–AD7/A7 pins is output through Port A. (Carefully check the generation
of CSADOUT1, and ensure that it is stable during the ALE pulse. When CSADOUT2 is
active, a write operation is performed (see note to Figure 5). The data on the input
AD0/A0–AD7/A7 pins flows out through Port A. When CSADIN and a read operation is
performed (depending on the mode of the RD/E or RD/E/DS, and WR/V
PP
or R/W pins), the
data on Port A flows out through the AD0/A0–AD7/A7 pins. In this operational mode, Port A
is tri-stated when none of the above-mentioned three conditions exist.
Port Functions
Configuration
Bits
No.
of Bits
Function
Port B is I/O or CS0– CS7
CPBF = 0, Port B pin is CS0 – CS7
CPBF = 1, Port B pin is I/O
Port B CMOS or Open Drain
CPBCOD = 0, CMOS output
CPBCOD = 1, open-drain output
Port C A16–A18 or CS8–CS10
CPCF = 0, Port C pin is A16–A18
CPCF = 1, Port C pin is CS8–CS10
Port C: A16–A19 Address or Logic Input
CADLOG = 0, Port C pin or A19/CSI is logic input
CADLOG = 1, Port C pin or A19/CSI is address input
Default:CMISER = 0
CMISER = 1, lower-power mode
CPBF
8
CPBCOD
8
CPCF
3
CADLOG
(Note 14)
4
CMISER
1
Table 5.
PSD3XX
Configuration
Bits (Cont.)
NOTES:
11. The PSD Development software will guide the user to the proper configuration choice.
12. In an unprogrammed or erased part, all configuration bits are 0.
13. PSD30X only.
14. PSD3X2/3X3 only.
15. PSD3X1 only.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD304R-12JI | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Field-Programmable Peripheral |
| PSD304R-12LI | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Field-Programmable Peripheral |
| PSD304R-12LM | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Field-Programmable Peripheral |
| PSD304R-12U | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Field-Programmable Peripheral |
| PSD304R-12UI | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Field-Programmable Peripheral |
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