![](http://datasheet.mmic.net.cn/260000/PSD313R_datasheet_15948888/PSD313R_32.png)
PSD3XX Famly
2-32
Security Mode in the PSD3XX locks the contents of the PAD A , PAD B and all the
configuration bits. The EPROM, SRAM, and I/O contents can be accessed only through
the PAD. The Security Mode can be set by the PSD Development or Programming
software. In window packages, the mode is erasable through UV full part erasure. In the
security mode, the PSD3XX contents cannot be copied on a programmer.
Symbol
Parameter
Condition
CERDIP
PLASTIC
With Respect to GND
Min
– 65
– 65
– 0.6
Max
+ 150
+ 125
+ 7
Unit
°C
°C
V
T
STG
Storage Temperature
Voltage on any Pin
Programming
Supply Voltage
V
PP
With Respect to GND
– 0.6
+ 14
V
V
CC
Supply Voltage
With Respect to GND
– 0.6
>
2000
+ 7
V
ESD Protection
V
Range
Temperature
V
CC
V
CC
Tolerance
Commercial
Industrial
Military
0° C to +70°C
–40° C to +85°C
–55° C to +125°C
+ 5 V
+ 5 V
+ 5 V
± 10%
± 10%
± 10%
Symbol
Parameter
Conditions
Min
Typ
Max Unit
V
CC
Supply Voltage
All Speeds
4.5
5
5.5
V
V
CC
Supply Voltage
PSD3XXL Versions Only,
All Speeds
3.0
3.3
5.5
V
The EPROM power consumption in the PSD is controlled by bit 3 in the PMMR0 – EPROM
CMiser. Upon reset the CMiser bit is OFF. This will cause the EPROM to be ON at all times
as long as CSI is enabled (low). The reason this mode is provided is to reduce the access
time of the EPROM by 10 ns relative to the low power condition when CMiser is ON.
If CSI is disabled (high) the EPROM will be deselected and will enter standby mode (OFF)
overriding the state of the CMiser.
If CMiser is set (ON) then the EPROM will enter the standby mode when not selected.
This condition can take place when CSI is high or when CSI is low and the EPROM is not
accessed. For example, if the MCU is accessing the SRAM, the EPROM will be
deselected and will be in low power mode.
An additional advantage of the CMiser is achieved when the PSD is configured in the by 8
mode (8 bit data bus). In this case an additional power savings is achieved in the EPROM
(and also in the SRAM) by turning off 1/2 of the array even when the EPROM is accessed
(the array is divided internally into odd and even arrays).
The power consumption for the different EPROM modes is given in the DC Characteristics
table under I
CC
(DC) EPROM Adder.
Security
Mode
EPROM
Absolute
Maximum
Ratings
26
Operating
Range
Recommended
Operating
Conditions
NOTE:
26.Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.