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參數(shù)資料
| 型號(hào)： | PSD413A2F |
| 英文描述： | Field Programmable Microcontroller Peripherals with Flash Memory(可編程邏輯，16K位SRAM,35個(gè)可編程I/O,通用PLD有59個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備與快閃記憶體（可編程邏輯，16K的位的SRAM，35余個(gè)可編程輸入/輸出，通用PLD的有59個(gè)輸入） |
| 文件頁(yè)數(shù)： | 55/98頁(yè) |
| 文件大?。?/td> | 365K |
| 代理商： | PSD413A2F |
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PSD413F Family
ADVANCE INFORMATION
Memory
Block
The PSD413F is a multi-chip module that includes a PSD4XX die and a 1 megabit Flash
memory die. The PSD4XX includes 8 Kbytes of OTP Boot EPROM; the Flash die provides
128 Kbytes of Flash memory. The OTP Boot EPROM is used for system boot up and for
storing the Flash memory programming algorithm. The Flash erase and programming
algorithms are compatible to the AMD Embedded Erase and Programming Algorithm
TM
.
The Flash memory can be erased or programmed while the microcontroller is executing
code from the Boot EPROM.
Chip selects for the memory blocks come from the DPLD and GPLD decoding logic and are
defined by the user in the PSDsoft software. Figure 29 shows the organization of the
Memory Block.
Boot EPROM
The chip select (CSBOOT) for the OTP Boot EPROM is generated from the DPLD address
decoder. The CSBOOT is defined in 8 Kbyte boundaries and should not overlap the Flash
memory address space.
Flash Memory
The 128 Kbyte of Flash memory space is divided into four 32 Kbyte blocks, each block
consisting of two 16 Kbyte sectors. ES3 – 0 are the chip selects for each block that are
defined in the DPLD at 32 Kbyte boundaries.
Five of the pins and macrocells on the PSD4XX die are reserved for the generation of Flash
memory control signals. Table 14 shows the name of the macrocells in the GPLD and the
corresponding pins on the PSD4XX die that are used. The address lines A15F, A16F and
the chip select CSF are generated based on the ES3 – 0 inputs to the GPLD. Refer to the
Application Notes in the PSD Applications Handbook on how to configure the PSD413F.
Refer to Appendix A for the operation and programming algorithm for the Flash memory.
SRAM
The SRAM has 16K bits of memory, organized as 2K x 8. The SRAM is enabled by the
chip select signal RS0 from the DPLD. The SRAM has a battery back-up (STBY) mode.
This back-up mode is automatically invoked when the V
CC
voltage drops under the Vstdby
voltage by approximately 0.7 V. The Vstdby voltage is connected only to the SRAM and
cannot be lower than 2.7 volts.
Memory Select Map
The Boot EPROM, Flash memory, and SRAM chip select equations are defined in the
ABEL file in terms of address and other DPLD inputs. The memory space for the Flash
chip select (ES0 – ES3) should not be larger than the 32K Flash block it is selecting.
The Boot EPROM block should not be larger than 8 Kbytes.
The following rules govern how the PSD413F memory selects/space are defined:
J
The Flash blocks address space cannot overlap among blocks.
J
The Flash blocks address space cannot overlap the Boot EPROM, the SRAM and I/O
address space.
J
SRAM and internal I/O address space cannot overlap.
J
SRAM and internal I/O space can overlap Boot EPROM space, with priority given to
SRAM or I/O. The portion of Boot EPROM which is overlapped cannot be accessed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD4235G2(中文) | Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片) |
| PSD4235G2 | Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片) |
| PSD4235G2 | FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (5V SUPPLY) |
| PSD4235G2V | -200V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-254AA package; A JANSR2N7426 with Standard Packaging |
| PSD4235G1-B-12J | Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4-16 | 制造商:Tamura Corporation of America 功能描述: |
| PSD4-20 | 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA |
| PSD4235G2-70U | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2-90UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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