參數(shù)資料
型號: PSD413A2F
英文描述: Field Programmable Microcontroller Peripherals with Flash Memory(可編程邏輯,16K位SRAM,35個可編程I/O,通用PLD有59個輸入)
中文描述: 現(xiàn)場可編程微控制器外圍設(shè)備與快閃記憶體(可編程邏輯,16K的位的SRAM,35余個可編程輸入/輸出,通用PLD的有59個輸入)
文件頁數(shù): 63/98頁
文件大?。?/td> 365K
代理商: PSD413A2F
PSD413F Family
6-63
ADVANCE INFORMATION
System
Configuration
The CSIOP signal, which is generated by the DPLD, selects the internal I/O devices or
registers. The CSIOP signal takes up 256 bytes of address space and is defined by the
user in the PSDSoft Software. The following is an address offset map for the various
devices relative to the CSIOP base address.
Register
Name
Address
Offset
Register
Name
Address
Offset
PAGE REGISTER
PMMR0
E0
B0
PMMR1
B1
Table 18. Register Address Offset
The following table is the address map offset of the I/O port registers.
Table 19. I/O Register Address Offset
Address Offset
Port C
Register Name
Port A
Port B
Port D
Port E
Data In
Control
Data Out
Direction
Open Drain
PLD – I/O
00
02
04
06
01
03
05
07
10
12
14
16
18
11
13
15
17
19
20
22
24
26
0A
0B
2A
2C
Macrocell Out
0C
0D
(PSD413A2F)
Register Name
Register Function
Data In
This Register is used to read the inputs on the port pins.
Control
A
0
sets the corresponding port pin in Address Out Mode.
A
1
sets the pin in MCU I/O Mode.
Data Out
Holds the output data in the MCU I/O Mode.
This register is used to control the data flow in the I/O ports.
A
0
sets the corresponding pin as an input pin.
A
1
sets the pin as an output pin.
Direction
Open Drain
A
0
sets the corresponding pin driver as a CMOS driver.
A
1
sets the pin driver as an Open Drain Driver.
PLD – I/O
A read only status register; a
1
indicates the corresponding pin
is configured as a PLD pin.
Macrocell Out
This register holds the outputs of the GPLD macrocells.
Page Register
A 4-bit register that supports paging.
PMMR0
PMMR1
Power management registers; enables the PSD4XX Power Down
Mode and other power saving configurations.
Table 20. Register Function
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參數(shù)描述
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