參數(shù)資料
型號： PSD4235G2
英文描述： Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片)
中文描述： Flash在系統(tǒng)可編程外設(shè)的16位微控制器（用于16位微控制器的閃速在系統(tǒng)可編程外圍芯片）
文件頁數(shù)： 13/114頁
文件大小： 567K
代理商： PSD4235G2
Beta Information
PSD4000 Series
9
Pin*
(TQFP
Pin Name Pkg.)
Type
Description
Reset
39
I
Active low input. Resets I/O Ports PLD Micro
Cells, some of
the configuration registers and JTAG registers. Must be active
at power up. Reset also aborts the Flash programming/erase
cycle that is in progress.
Port A, PA0-7. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port
2. CPLD Micro
Cell (McellA0-7) output.
3. Latched, transparent or registered PLD inputs (can also be
PLD input for address A16 and above).
Port B, PB0-7. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. CPLD Micro
Cell (McellB0-7 output.
3. Latched, transparent or registered PLD inputs (can also be
PLD input for address A16 and above).
Port C, PC0-7. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. External chip select (ECS0-7) output.
3. Latched, transparent or registered PLD inputs (can also be
PLD input for address A16 and above).
Port D pin PD0 can be configured as:
1. ALE or AS input — latches addresses on ADIO0-15 pins
2. AS input — latches addresses on ADIO0-15 pins on the
rising edge.
3. MCU I/O
4. Transparent PLD input (can also be PLD input for address
A16 and above).
Port D pin PD1 can be configured as:
1. MCU I/O
2. Transparent PLD input (can also be PLD input for address
A16 and above).
3. CLKIN clock input — clock input to the CPLD
Micro
Cells, the APD power down counter and CPLD
AND Array.
Port D pin PD2 can be configured as:
1. MCU I/O
2. Transparent PLD input (can also be PLD input for address
A16 and above).
3. CSI input — chip select input. When low, the CSI enables
the internal PSD memories and I/O. When high, the
internal memories are disabled to conserve power. CSI
trailing edge can get the part out of power-down mode.
Port D pin PD3 can be configured as:
1. MCU I/O
2. Transparent PLD input (can also be PLD input for address
A16 and above).
3. WRH — for 16-bit data bus, write to high byte, active low.
Port E, PE0. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. Latched address output.
3. TMS input for JTAG-ISP interface.
PA0-PA7
51-58
I/O
CMOS
or Open
Drain
PB0-PB7
61-68
I/O
CMOS
or Open
Drain
PC0-PC7 41-48
I/O
CMOS
or Slew
Rate
PD0
79
I/O
CMOS
or Open
Drain
PD1
80
I/O
CMOS
or Open
Drain
PD2
1
I/O
CMOS
or Open
Drain
PD3
2
I/O
CMOS
or Open
Drain
PE0
71
I/O
CMOS
or Open
Drain
Table 5.
PSD4000
Pin
Descriptions
(cont.)
相關(guān)PDF資料
PDF描述
PSD4235G2 FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (5V SUPPLY)
PSD4235G2V -200V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-254AA package; A JANSR2N7426 with Standard Packaging
PSD4235G1-B-12J Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
PSD4235F2-A-12J Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
PSD4235G2-A-12J Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD4235G2-70U 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD4235G2-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2-90UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-12UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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