參數(shù)資料
型號： PSD4235G2
英文描述： Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片)
中文描述： Flash在系統(tǒng)可編程外設(shè)的16位微控制器（用于16位微控制器的閃速在系統(tǒng)可編程外圍芯片）
文件頁數(shù)： 44/114頁
文件大?。?/td> 567K
代理商： PSD4235G2
PSD4000 Series
Beta Information
40
9.2.2.6 Input Micro
Cells (IMCs)
The CPLD has 24 IMCs, one for each pin on Ports A, B, and C. The architecture of the IMC
is shown in Figure 13. The IMCs are individually configurable, and can be used as a latch,
register, or to pass incoming Port signals prior to driving them onto the PLD input bus. The
outputs of the IMCs can be read by the microcontroller through the internal data bus.
The enable for the latch and clock for the register are driven by a multiplexer whose inputs
are a product term from the CPLD AND array or the MCU address strobe (ALE/AS). Each
product term output is used to latch or clock four IMCs. Port inputs 3-0 can be controlled by
one product term and 7-4 by another.
Configurations for the IMCs are specified by PSDsoft. Outputs of the IMCs can be read by
the MCU via the IMC buffer. See the I/O Port section on how to read the IMCs.
IMCs can use the address strobe to latch address bits higher than A15. Any latched
addresses are routed to the PLDs as inputs.
IMCs are particularly useful with handshaking communication applications where two
processors pass data back and forth through a common mailbox. Figure 14 shows a typical
configuration where the Master MCU writes to the Port A Data Out Register. This, in turn,
can be read by the Slave MCU via the activation of the “Slave-Read” output enable product
term. The Slave can also write to the Port A IMCs and the Master can then read the IMCs
directly. Note that the “Slave-Read” and “Slave-Wr” signals are product terms that are
derived from the Slave MCU inputs RD, WR, and Slave_CS.
The
PSD4000
Functional
Blocks
(cont.)
OUTPUT
MICRO
CELLS A
AND
MICRO
CELL B
PT
PT
FEEDBACK
A
P
PORT
DRIVER
I/O PIN
INTERNAL DATA BUS
DIRECTION
REGISTER
MUX
MUX
ALE/AS
PT
Q
Q
D
D
G
LATCH
INPUT MICRO
CELL
ENABLE (.OE)
D FF
INPUT MICRO
CELL_ RD
Figure 13. Input Micro
Cell
相關(guān)PDF資料
PDF描述
PSD4235G2 FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (5V SUPPLY)
PSD4235G2V -200V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-254AA package; A JANSR2N7426 with Standard Packaging
PSD4235G1-B-12J Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
PSD4235F2-A-12J Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
PSD4235G2-A-12J Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD4235G2-70U 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD4235G2-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2-90UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-12UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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